一個基於數位時間轉換器基礎的快速鎖定除小數型次取樣鎖相迴路

Abstract

本論文提出兩個晶片，一個是操作在4千萬赫茲、解析度為2.2萬億分之一秒的時間數位轉換器，另一個是輸出在5.4到6.2億赫茲、700千赫茲頻寬，參考頻率為4千萬赫茲的除小數型次取樣相位鎖定迴路，兩個晶片皆實現在40奈米製程。數位時間轉換器使用電容陣列數位類比轉換器固定斜率式的架構為基礎，加入電阻式源級負回授來增加線性度；除小數型次取樣相位鎖定迴路的電路中，數位時間轉換器再進一步改良成分段型的架構以減少製程變異因素與晶片外控制，一個極小的靜態區間產生器被提出來加快鎖定速度，與一個以緩衝器為基礎的雙迴路濾波器技巧被提出，來分開頻率相位鎖定迴路與次取樣相位鎖定迴路並進一步增快鎖定速度。 本文提出時間數位轉換器的積分非線性為2.4有效位元，在0.9V的供電下功率消耗為76uW，提出次取樣相位鎖定迴路有短時間穩定與重新鎖定，並在量測中顯現其可行性，次取樣相位鎖定迴路在輸出頻率為5.57億赫茲下，量測到的相位雜訊為-90 dBc/Hz和-127 dBc/Hz分別在偏移頻率為10萬赫茲與1千萬赫茲，被積分的相位雜訊為1.1億萬分之一秒的抖動量，功率消耗為9.5毫安培在0.9與1.8的供電下，質量因數為-229 dB與-236dB分別在除小數以及除整數型下。

This thesis presents two ICs. One is a digital-to-time converter (DTC) operating at 40 MHz with a resolution of 2.2 ps. The other is a subsampling phase-locked loop (SSPLL) operating in the frequency range of 5.4 to 6.2 GHz with a bandwidth of 700 kHz and a reference frequency of 40 MHz. Both chips are implemented in CMOS 40nm process. The DTC – Chip 1 is based on a C-DAC constant-slope architecture, with the addition of resistance source degeneration to enhance linearity. In the SSPLL - Chip 2, the DTC is further improved with a segmented architecture. To accelerate the locking speed of SSPLL, a mini dead zone generator is proposed. Besides, a buffer-based dual-loop filter technique separating FLL and SSL is proposed, further enhancing the locking speed. This thesis presents a DTC with INL of 2.4 LSB and power consumption of 76uW under supply of 0.9V. The proposed SSPLL has short settling and re-locking time with a fast-locking time technique. The measurement of locking behavior shows its feasibility. The SSPLL measured phase noise is -90 dBc/Hz and -127 dBc/Hz at offset frequencies of 100 kHz and 10 MHz, respectively, when operating at an output frequency of 5.57 GHz. The integrated phase jitter is 1.1ps, and the power consumption is 9.5 mW with the supply of 0.9V and 1.8V. The gm stage, charge pump, opamp, and VCO are under supply of 1.8V, while the other blocks are operated at 0.9V. The FoM is -229dB and -236dB, respectively, in the fractional mode and integer mode of the proposed frequency synthesizer.