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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89075完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | zh_TW |
| dc.contributor.advisor | Hsin-Shu Chen | en |
| dc.contributor.author | 黃晨怡 | zh_TW |
| dc.contributor.author | Chen-Yi Huang | en |
| dc.date.accessioned | 2023-08-16T17:01:33Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-08-16 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-08-09 | - |
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Liu, "A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time," 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019, pp. 95-98 [ 11 ] D. Liao, F. F. Dai, B. Nauta and E. A. M. Klumperink, "A 2.4-GHz 16-phase sub-sampling fractional-N PLL with robust soft loop switching," IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 715-727, Mar. 2018 [ 12 ] M. H. Perrott, M. D. Trott and C. G. Sodini, "A modeling approach for /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers allowing straightforward noise analysis," in IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 1028-1038, Aug. 2002 [ 13 ] Markulic, N. (2018). Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission. [ 14 ] Behzad Razavi (2012). RF Microelectronics, Second Edition. [ 15 ] Po-Chun Huang “The Design and Analysis of a Low-Noise Divider-less Fractional-N Synthesizer with Sub-Sampling Phase-Locked Loop Architecture” 2014. [ 16 ] Alan V. Oppenheim, Ronald W. Schafer, Discrete-Time Signal Processing, Prentice Hall, 1999. [ 17 ] K. Raczkowski, N. Markulic, B. Hershberg and J. Craninckx, "A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter," in IEEE Journal of Solid-State Circuits, vol. 50, no. 5, pp. 1203-1213, May 2015 [ 18 ] W. -S. Chang, P. -C. Huang and T. -C. Lee, "A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector," in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2964-2975, Dec. 2014 [ 19 ] P. Chen, F. Zhang, Z. Zong, S. Hu, T. Siriburanon and R. B. Staszewski, "A 31- $\mu$ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 54, no. 11, pp. 3075-3085, Nov. 2019 [ 20 ] J. Z. Ru, C. Palattella, P. Geraedts, E. Klumperink and B. Nauta, "A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging," in IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1412-1423, June 2015 [ 21 ] Behzad Razavi, "A Family of LowPower Truly Modular Programmable Dividers in Standard 0.35m CMOS Technology," in Phase-Locking in High-Performance Systems: From Devices to Architectures , IEEE, 2003, pp.346-352 [ 22 ] D. Tasca, M. Zanuso, G. Marzin, S. Levantino, C. Samori and A. L. Lacaita, "A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power," in IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2745-2758, Dec. 2011 [ 23 ] A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," in IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998 [ 24 ] B. d. Muer and M. Steyaert, CMOS fractional-N synthesizers : design for high spectral purity and monolithic integration. Boston: Kluwer Academic Publishers, 2003. [ 25 ] X. Gao, E. A. M. Klumperink, P. F. J. Geraedts and B. Nauta, "Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 2, pp. 117-121, Feb. 2009 [ 26 ] C. Palattella, E. A. M. Klumperink, J. Z. Ru and B. Nauta, "A Sensitive Method to Measure the Integral Nonlinearity of a Digital-to-Time Converter Based on Phase Modulation," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 8, pp. 741-745, Aug. 2015 | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89075 | - |
| dc.description.abstract | 本論文提出兩個晶片，一個是操作在4千萬赫茲、解析度為2.2萬億分之一秒的時間數位轉換器，另一個是輸出在5.4到6.2億赫茲、700千赫茲頻寬，參考頻率為4千萬赫茲的除小數型次取樣相位鎖定迴路，兩個晶片皆實現在40奈米製程。數位時間轉換器使用電容陣列數位類比轉換器固定斜率式的架構為基礎，加入電阻式源級負回授來增加線性度；除小數型次取樣相位鎖定迴路的電路中，數位時間轉換器再進一步改良成分段型的架構以減少製程變異因素與晶片外控制，一個極小的靜態區間產生器被提出來加快鎖定速度，與一個以緩衝器為基礎的雙迴路濾波器技巧被提出，來分開頻率相位鎖定迴路與次取樣相位鎖定迴路並進一步增快鎖定速度。
本文提出時間數位轉換器的積分非線性為2.4有效位元，在0.9V的供電下功率消耗為76uW，提出次取樣相位鎖定迴路有短時間穩定與重新鎖定，並在量測中顯現其可行性，次取樣相位鎖定迴路在輸出頻率為5.57億赫茲下，量測到的相位雜訊為-90 dBc/Hz和-127 dBc/Hz分別在偏移頻率為10萬赫茲與1千萬赫茲，被積分的相位雜訊為1.1億萬分之一秒的抖動量，功率消耗為9.5毫安培在0.9與1.8的供電下，質量因數為-229 dB與-236dB分別在除小數以及除整數型下。 | zh_TW |
| dc.description.abstract | This thesis presents two ICs. One is a digital-to-time converter (DTC) operating at 40 MHz with a resolution of 2.2 ps. The other is a subsampling phase-locked loop (SSPLL) operating in the frequency range of 5.4 to 6.2 GHz with a bandwidth of 700 kHz and a reference frequency of 40 MHz. Both chips are implemented in CMOS 40nm process. The DTC – Chip 1 is based on a C-DAC constant-slope architecture, with the addition of resistance source degeneration to enhance linearity. In the SSPLL - Chip 2, the DTC is further improved with a segmented architecture. To accelerate the locking speed of SSPLL, a mini dead zone generator is proposed. Besides, a buffer-based dual-loop filter technique separating FLL and SSL is proposed, further enhancing the locking speed.
This thesis presents a DTC with INL of 2.4 LSB and power consumption of 76uW under supply of 0.9V. The proposed SSPLL has short settling and re-locking time with a fast-locking time technique. The measurement of locking behavior shows its feasibility. The SSPLL measured phase noise is -90 dBc/Hz and -127 dBc/Hz at offset frequencies of 100 kHz and 10 MHz, respectively, when operating at an output frequency of 5.57 GHz. The integrated phase jitter is 1.1ps, and the power consumption is 9.5 mW with the supply of 0.9V and 1.8V. The gm stage, charge pump, opamp, and VCO are under supply of 1.8V, while the other blocks are operated at 0.9V. The FoM is -229dB and -236dB, respectively, in the fractional mode and integer mode of the proposed frequency synthesizer. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-08-16T17:01:33Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-08-16T17:01:33Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 論文口試委員審定書 i
致謝 ii 摘要 iii Abstract iv CONTENTS v LIST OF FIGURES ix LIST OF TABLES xvi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Fundamentals of Phase-Locked Loop 4 2.1 Introduction 4 2.2 Type II Charge Pump PLL 5 2.3 Fractional-N PLL 7 2.4 Subsampling Phase-Locked Loop 9 2.5 Phase Compensation and Digital-to-Time Converter 17 2.6 Summary 20 Chapter 3 Proposed DTC-based Fractional-N Sub-sampling Phase-locked Loop with Fast Locking Time 22 3.1 Proposed Architecture 24 3.1.1 10-bit C-DAC constant slope DTC with resistance source degeneration – Chip 1 24 3.1.2 DTC-based Fractional-N Subsampling PLL – Chip 2 27 3.1.2.1 10-bit Segmented C-DAC constant slope DTC 29 3.1.2.2 Mini dead-zone technique and Buffer-based dual loop filter 32 3.2 Circuit Implementation 39 3.2.1 10-bit C-DAC constant slope DTC with resistance source degeneration – Chip 1 39 3.2.2 DTC-based Fractional-N Subsampling PLL – Chip 2 44 3.2.2.1 Subsampling phase detector and Gm cell 44 3.2.2.2 Segmented Constant-slope C-DAC DTC 47 3.2.2.3 DTC Modulator and Gain background calibration 52 3.2.2.4 Frequency-Locked Loop 55 3.2.2.5 PFD with mini dead-zone generator / Charge Pump 55 3.2.2.6 Multi-modulus Divider 57 3.2.2.7 Voltage-controlled oscillator(VCO) 58 3.2.2.8 OPAMP in dual loop 62 3.2.2.9 Loop filter 63 3.3 Behavior Model and Simulation 64 3.4 Circuit Simulation Results 66 3.4.1 10-bit C-DAC constant slope DTC with resistance source degeneration – Chip 1 67 3.4.2 DTC-based Fractional-N Subsampling PLL – Chip 2 69 3.4.2.1 Segmented DTC 69 3.4.2.2 Voltage-controlled Oscillator 71 3.4.2.3 Mini-dead Zone with Buffer-based Dual Loop Transient Simulation 72 3.4.2.4 Gain Background Calibration 76 3.4.2.5 OPAMP Simulation 77 3.5 Summary 79 Chapter 4 Noise Model and Behavior Simulation 80 4.1 Linear Noise Model and Phase Noise 80 4.1.1 Subsampling Loop Noise Model 80 4.1.2 Subsampling Loop Phase Noise Calculation 82 4.1.2.1 Reference and DTC Noise 82 4.1.2.2 DTC Quantization Noise 83 4.1.2.3 Sub-sampling Phase Detector Noise 84 4.1.2.4 Gm Stage Noise 84 4.1.2.5 Loop Filter Noise 85 4.1.2.6 VCO Noise 85 4.1.2.7 Total Noise in Linear Model 86 4.2 Nonlinear Noise Model 87 4.2.1 Gain error 89 4.2.2 INL error 89 4.3 Behavior Model and Block Simulation Results 90 4.3.1 Phase Noise Simulation 90 4.3.1.1 VCO phase noise 90 4.3.1.2 DTC phase noise 91 4.3.1.3 SSPD/GM phase noise 92 4.3.1.4 Loop Filter Noise 93 4.3.1.5 System Bode Plot 94 4.3.1.6 Overall Phase Noise Calculation in MATLAB 96 4.4 Summary 100 Chapter 5 Measurement Results 101 5.1 Printed Circuit Board Design 101 5.2 Measurement Environment 104 5.2.1 10-bit C-DAC constant slope DTC with resistance source degeneration – Chip 1 104 5.2.2 DTC-based Fractional-N Subsampling PLL – Chip 2 107 5.3 Measurement Results 108 5.3.1 10-bit C-DAC constant slope DTC with resistance source degeneration – Chip 1 108 5.3.2 DTC-based Fractional-N Subsampling PLL – Chip 2 111 5.3.2.1 Area and Power Dissipation 111 5.3.2.2 Locking Time 116 5.3.2.3 Phase Noise 120 5.4 Comparison 125 5.5 Summary 127 Chapter 6 Conclusion 129 6.1 Thesis Summary 129 6.2 Future Work 130 REFERENCE 132 | - |
| dc.language.iso | en | - |
| dc.subject | 極小靜態區間 | zh_TW |
| dc.subject | 快速鎖定 | zh_TW |
| dc.subject | 次取樣相位鎖定迴路 | zh_TW |
| dc.subject | 數位時間轉換器 | zh_TW |
| dc.subject | 除小數型頻率合成器 | zh_TW |
| dc.subject | subsampling phase-locked loop (SSPLL) | en |
| dc.subject | digital-to-time converter (DTC) | en |
| dc.subject | fractional frequency synthesizer | en |
| dc.subject | mini dead zone | en |
| dc.subject | fast-locking | en |
| dc.title | 一個基於數位時間轉換器基礎的快速鎖定除小數型次取樣鎖相迴路 | zh_TW |
| dc.title | A DTC-based Fractional-N Sub-sampling Phase-locked Loop with Fast Locking Time | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 林宗賢;劉宗德;王君弘 | zh_TW |
| dc.contributor.oralexamcommittee | Tsung-Hsien Lin;Tsung-Te Liu;Jyun-Hong Wang | en |
| dc.subject.keyword | 數位時間轉換器,次取樣相位鎖定迴路,除小數型頻率合成器,快速鎖定,極小靜態區間, | zh_TW |
| dc.subject.keyword | digital-to-time converter (DTC),subsampling phase-locked loop (SSPLL),fractional frequency synthesizer,fast-locking,mini dead zone, | en |
| dc.relation.page | 135 | - |
| dc.identifier.doi | 10.6342/NTU202303842 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2023-08-11 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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