用於類比數位轉換器抖動誤差消除之時間數位轉換器

Abstract

在現今高速､高精準度的類比數位轉換中，其對取樣時脈抖動之規格要求日益嚴苛，通常需要達到數個微微秒之內，故難以在晶片中產生符合規格之時脈。在這篇論文中，提出了一種適用於消除類比數位轉換器中之抖動誤差的方法。在此種方法中，信號每個取樣點之斜率為一重要的關鍵參數。隨著信號頻率增加，由此演算法所計算出之斜率會開始受到sinc函數的影響而導致失真。此時查表法可以用來補償這種效應，使得系統能操作在接近Nyquist-rate之頻率。 在所提出的架構中，需要一時間數位轉換器來進行數位化抖動誤差消除的演算法。此外，此時間數位轉換器必須擁有較大的動態範圍與高解析度，如此才能涵蓋峰對峰抖動範圍同時維持準確度。在此論文中，設計了一個10微微秒以及5.12奈秒動態範圍之基於倍化式延時鎖定迴路(multiplying DLL)局部被動內插(local passive interpolation)之時間數位轉換器。電路製作使用標準90奈米互補金氧半導體邏輯製程，所設計的時間數位轉換器在1伏特電壓源供應下，功率消耗為6毫瓦。此電路的晶片面積為0.17毫米平方。

The requirement of sampling clock jitter becomes rigorous in the high-speed and high-precision analog-to-digital date conversion, usually around few pico-seconds, which is unreachable for the on-chip clock generation. A method is proposed to cancel the jitter-induced errors in ADC. One of the key parameters needed here is the derivative of each sampled points. The derivative calculated from the algorithm is distorted by a sinc function as the signal frequency gets higher. A look-up table method is applied to compensate the distortion factor which makes the system to operate well near Nyquist rate.

In this architecture, a time-to-digital converter (TDC) is desired to adopt the jitter cancellation algorithm in the digital domain. Besides, this TDC need to be wide dynamic range and high precision in order to cover the peak-to-peak jitter variation while maintain the accuracy. In this thesis, an MDLL-based TDC with local passive interpolation which has 10ps resolution and 5.12ns dynamic range is designed. Fabricated in a 90-nm CMOS technology, the TDC consumes 6.0mW from a 1-V power supply while the active area is only 0.017mm2.