利用突變分析認證功能驗證環境以增強基於模擬的驗證流程

Abstract

由於集成電路的複雜性呈指數增長，功能驗證已成為IC設計驗證流程的重要部分。功能驗證的困難隨著市場競爭日趨激烈、產品上市時間的壓力而增加。這些挑戰需要使用高質量的測試平臺，才能夠徹底驗證設計。而要找出一個錯誤，測試平台必須模擬各種可能性，將錯誤行為傳播到一些檢查點，並在這些檢查點使用檢查器進行觀測。在主要的驗證方法中，一般人會採用覆蓋率指標評估測試平台，例如代碼覆蓋率和功能覆蓋率。然而，這些指標主要關注錯誤的激活，而忽視了錯誤的傳播和檢測階段，這可能導致一些錯誤未被檢測，而對系統構成潛在的風險。所以完整的驗證流程需要一個額外的指標，稱之為突變覆蓋率，來補充現有的指標並解決這些驗證差距。這篇論文提出了一種方法，使用突變覆蓋率的反饋來改進基於模擬的功能驗證，從而提高驗證環境(VE)的質量。我們在一個已經具有成熟驗證的複雜設計上進行實驗，結果顯示即使在這個驗證已經相對完整的設計上，我還們是可以持續地將驗證質量大幅提升，並且同時揭示了現有驗證環境中的幾個漏洞。

Functional verification has become an integral part of the IC design verification flow due to the exponential growth in the size and complexity of integrated circuits. The difficulty of functional verification increases in tandem with the mounting pressure to swiftly release products amidst intense market competition. Due of the aforementioned challenges, a top-notch testbench that can completely verify the design is required. A bug must be stimulated, propagated to some checked sites, and then detected there using checkers for the testbench to reveal it. In common verification methodologies, the success of the test vectors produced by the testbench is assessed using coverage metrics, specifically code coverage and functional coverage. These metrics, however, mainly focus on bug activation, leaving significant gaps in addressing propagation and detection stages. These gaps could result in undetected bugs, posing potential system risks. An additional metric, called mutation coverage, is needed to complement the existing metrics and address these verification gaps. This thesis proposes a methodology to improve simulation-based functional verification using mutation coverage feedback, thereby enhancing the quality of the verification environment (VE). Experimental results on a complex digital design with mature verification efforts demonstrate substantial quality improvement and reveal several vulnerabilities in the existing verification environment.