透過順序設計映射進行 RTL Bug 定位

Abstract

在設計積體電路時，快速的找出設計中的錯誤並修正是提高工程師產能的重要議題，然而往往根據測試資料獲得的波形檔的時脈數都十分的長，想要快速的找出錯誤發生的位置成為一個難題。這份研究希望可以開發一套工具，善加利用現有的各種波形檔，經過一些時序上的比對並分析特定訊號出現的規律，將正確的標準波形檔與我們預期發生錯誤的波形檔自動的疊合並提示何處可能發生了錯誤，同時產生一份新的波形檔，使工程師可以使用任何現有的波形顯示器一目瞭然的看出錯誤的位置與數值，並快速的修復錯誤。 經由使用我們的工具可以將工程師所需要分析的波形檔範圍降為原先所需的1%以下。同時我們的工具也只需數分鐘即可分析完畢來自數千行 RTL並且有數萬時脈的波形檔。

In integrated circuit design, quickly identifying and rectifying errors is a crucial aspect to enhance engineer productivity. However, the waveform files obtained from test data often come with lengthy timeframes, making it challenging to pinpoint error locations. This research aims to develop a tool that effectively utilizes various waveform files, performs temporal comparisons and analyzes patterns of specific signal occurrences. The tool automatically overlays the correct waveform with the erroneous one, highlights potential error locations, and generates a new waveform file. Engineers can then use any existing waveform viewer to quickly identify error locations and values and thus facilitate rapid error rectification. By utilizing our tool, engineers can reduce the size of the waveform file for analysis to less than 1%. Moreover, our tool can analyze waveform files from thousands of lines of RTL with tens of thousands of cycles in a matter of minutes.