Please use this identifier to cite or link to this item:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/88888Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚 | zh_TW |
| dc.contributor.advisor | Chung-Yang Huang | en |
| dc.contributor.author | 莊博翰 | zh_TW |
| dc.contributor.author | Bo-Han Chuang | en |
| dc.date.accessioned | 2023-08-16T16:13:00Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-08-16 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-08-08 | - |
| dc.identifier.citation | [1]Chang, Kai-hui, et al. "Incremental verification with error detection, diagnosis, and visualization." IEEE Design & Test of Computers 26.2 (2009): 34-43.
[2]Bartenstein, Thomas, et al. "Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm." Proceedings International Test Conference 2001 (Cat. No. 01CH37260). IEEE, 2001. [3]Dehbashi, Mehdi, and Goerschwin Fey. "Debug automation for synchronization bugs at RTL." 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems. IEEE, 2014. [4]B. Keng, S. Safarpour and A. Veneris, "Automated debugging of SystemVerilog assertions," 2011 Design, Automation & Test in Europe, Grenoble, France, 2011, pp. 1-6, doi: 10.1109/DATE.2011.5763057. [5]Mirzaeian, Saeed, Feijun Zheng, and K-T. Tim Cheng. "RTL error diagnosis using a word-level SAT-solver." 2008 IEEE International Test Conference. IEEE, 2008. [6]Iyer, Vighnesh, et al. "RTL bug localization through LTL specification mining (WIP)." Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design. 2019. [7]Kumar, Binod, et al. "Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41.12 (2022): 5709-5721. [8]N. Veira, Z. Poulos and A. Veneris, "Suspect set prediction in RTL bug hunting," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2018, pp. 1544-1549, doi: 10.23919/ DATE.2018.8342261. [9]H. Mangassarian, B. Le and A. Veneris, "Debugging RTL Using Structural Dominance," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, pp. 153-166, Jan. 2014, doi: 10.1109/ TCAD.2013.2278491. [10]Jiang, Tai-Ying, C-NJ Liu, and Jing-Yang Jou. "Effective error diagnosis for RTL designs in HDLs." Proceedings of the 11th Asian Test Symposium, 2002. (ATS'02).. IEEE, 2002. [11]M. F. Ali, S. Safarpour, A. Veneris, M. S. Abadir and R. Drechsler, "Post- verification debugging of hierarchical designs," ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., San Jose, CA, USA, 2005, pp. 871-876, doi: 10.1109/ICCAD.2005.1560184. [12]Rajashekar, Sanjay. A study on Machine Learning-based Hardware Bug Localization. Diss. 2020. [13]A. DeOrio, Q. Li, M. Burgess and V. Bertacco, "Machine learning-based anomaly detection for post-silicon bug diagnosis," 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2013, pp. 491-496, doi: 10.7873/DATE.2013.112. [14]A. DeOrio, Q. Li, M. Burgess and V. Bertacco, "Machine learning-based anomaly detection for post-silicon bug diagnosis," 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2013, pp. 491-496, doi: 10.7873/DATE.2013.112. [15]Pal, D., Dodeja, V., Kumar, A. S., & Vasudevan, S. GOLDMINE: A tool for enhancing verification productivity. [16]Danese, Alessandro, Tara Ghasempouri, and Graziano Pravadelli. "Automatic extraction of assertions from execution traces of behavioural models." 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2015 [17]V. Athavale, Sai Ma, S. Hertz and S. Vasudevan, "Code coverage of assertions using RTL source code analysis," 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, 2014, pp. 1-6, doi: 10.1145/2593069.2593108. [18]Huang, Shao-Lun, et al. "Match and replace: A functional ECO engine for multierror circuit rectification." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32.3 (2013): 467-478. [19]K. -H. Chang, V. Bertacco and I. L. Markov, "Simulation-Based Bug Trace Minimization With BMC-Based Refinement," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 1, pp. 152-165, Jan. 2007, doi: 10.1109/TCAD.2006.882511. [20]Backurs, Arturs, and Piotr Indyk. "Edit distance cannot be computed in strongly subquadratic time (unless SETH is false)." Proceedings of the forty- seventh annual ACM symposium on Theory of computing. 2015. [21]Myers, Eugene W. "An O (ND) difference algorithm and its variations." Algorithmica 1.1-4 (1986): 251-266. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/88888 | - |
| dc.description.abstract | 在設計積體電路時，快速的找出設計中的錯誤並修正是提高工程師產能的重要議題，然而往往根據測試資料獲得的波形檔的時脈數都十分的長，想要快速的找出錯誤發生的位置成為一個難題。這份研究希望可以開發一套工具，善加利用現有的各種波形檔，經過一些時序上的比對並分析特定訊號出現的規律，將正確的標準波形檔與我們預期發生錯誤的波形檔自動的疊合並提示何處可能發生了錯誤，同時產生一份新的波形檔，使工程師可以使用任何現有的波形顯示器一目瞭然的看出錯誤的位置與數值，並快速的修復錯誤。
經由使用我們的工具可以將工程師所需要分析的波形檔範圍降為原先所需的1%以下。同時我們的工具也只需數分鐘即可分析完畢來自數千行 RTL並且有數萬時脈的波形檔。 | zh_TW |
| dc.description.abstract | In integrated circuit design, quickly identifying and rectifying errors is a crucial aspect to enhance engineer productivity. However, the waveform files obtained from test data often come with lengthy timeframes, making it challenging to pinpoint error locations. This research aims to develop a tool that effectively utilizes various waveform files, performs temporal comparisons and analyzes patterns of specific signal occurrences. The tool automatically overlays the correct waveform with the erroneous one, highlights potential error locations, and generates a new waveform file. Engineers can then use any existing waveform viewer to quickly identify error locations and values and thus facilitate rapid error rectification.
By utilizing our tool, engineers can reduce the size of the waveform file for analysis to less than 1%. Moreover, our tool can analyze waveform files from thousands of lines of RTL with tens of thousands of cycles in a matter of minutes. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-08-16T16:13:00Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-08-16T16:13:00Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 ii ABSTRACT iii CONTENTS iv 圖目錄 vi 表目錄 viii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Related Work 2 1.3 Contributions 4 Chapter 2 Background Knowledge 5 2.1 Bug diagnosing in IC Design Flow 5 2.2 Assertion-Based Verification 6 2.3 Debugging via VCD waveform 8 Chapter 3 Overview of Bug Localization 10 3.1 How Our Tool Facilitates Bug Identification in Design 10 3.2 The Architecture of Our Framework 11 3.3 Assumptions Regarding the Design 12 Chapter 4 Algorithm of Sequential Matching 15 4.1 Brief Introduction of Sequential Matching 15 4.2 Baseline Dynamic Programming Solution 17 4.3 One to Many Matching 19 4.4 Linear Time Upper Bound Calculation 21 4.5 Zoom In Zoom Out Algorithm 22 Chapter 5 Algorithm of Data-Control State Detection 25 5.1 Data-Control State Detection Overview 25 5.2 Controlling Set Collection 27 5.3 Data-Control state analyzing 28 5.4 Linear Time Rematching Based on Data-Control State 30 Chapter 6 Automatic Diagnosing the Bug 31 6.1 Analyze the Fail VCD with Sequential Matching Information 31 6.2 How to Identify Potential Bug 33 6.3 Merge DUV & Golden VCD 34 6.4 How Designers Utilize the Merged VCD 35 Chapter 7 Experimental Results 37 7.1 A Brief Overview of the Designs 37 7.2 Experimental Results 45 Chapter 8 Conclusion 48 8.1 Summary 48 8.2 Future Work 49 Reference 50 Appendix I 52 Appendix II 53 | - |
| dc.language.iso | en | - |
| dc.subject | 高階語言 | zh_TW |
| dc.subject | 錯誤偵測 | zh_TW |
| dc.subject | 波形檔 | zh_TW |
| dc.subject | 序列比對 | zh_TW |
| dc.subject | 積體電路設計 | zh_TW |
| dc.subject | VCD file | en |
| dc.subject | Bug Diagnosing | en |
| dc.subject | high-level language | en |
| dc.subject | integrated circuit design | en |
| dc.subject | Sequence Matching | en |
| dc.title | 透過順序設計映射進行 RTL Bug 定位 | zh_TW |
| dc.title | RTL Bug Localization via Sequential Design Matching | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 李建模;黃紹倫;莊咸和;廖士賢 | zh_TW |
| dc.contributor.oralexamcommittee | Chien-Mo Li;Shao-Lun Huang;Hsien-Ho Chuang;Peter Liao | en |
| dc.subject.keyword | 錯誤偵測,波形檔,序列比對,積體電路設計,高階語言, | zh_TW |
| dc.subject.keyword | Bug Diagnosing,VCD file,Sequence Matching,integrated circuit design,high-level language, | en |
| dc.relation.page | 53 | - |
| dc.identifier.doi | 10.6342/NTU202303127 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2023-08-10 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| Appears in Collections: | 電子工程學研究所 | |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-111-2.pdf Access limited in NTU ip range | 8.42 MB | Adobe PDF |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.