應用在 FMCW雷達的 24-GHz 高整合CMOS 收發機

Abstract

過去十年，毫米波雷達收發機有著顯著的發展，及被廣泛的使用在各種不同的應用。以長距離偵測雷達而言，76-77 GHz 的雷達收發機被使用在汽車的主動式車距調節巡航系統中，以偵測長距離的物體或車輛來防止碰撞和車禍的發生。短距離雷達收發機，則是操作在 22-29 GHz 以及 77-81 GHz。同樣的也被廣泛的使用在許多的應用中，例如：汽車的自動車尾門、汽車的盲點偵測系統、車門開啟警示系統等。其中76-77 GHz 及 77-81 GHz的頻段，被美國聯邦通訊委員會特別保留為車用雷達頻段 (可用於長距離或短距離偵測)。大部分的毫米波雷達收發機會使用 SiGe 的製程，或是 BiCMOS 的製程技術來達到高增益、高頻率操作的需求。但隨著 CMOS 製程技術的發展，近年來，可以看到越來越多的 CMOS 毫米波雷達收發機研究結果。在我們此次的研究中，呈現了使用 55-nm CMOS製程來製作的一個應用在頻率調變連續波(Frequency-Modulated Continuous Wave, FMCW) 雷達的 24-GHz 高整合CMOS 收發機。同時採用 5-mm × 5-mm 的四方平面無引腳封裝(Quad-Flat No-leads, QFN). 此顆應用在頻率調變連續波雷達的24-GHz 高整合CMOS 收發機，是以 2.5 V為電源供應電壓，總消耗電流為 344 mA，裸晶的面積為 7.84 mm^2.

Over the past decade, the Millimeter-Wave (mm-Wave) radar transceivers (sensors) have been significantly developed and widely used in many applications. For the Long-Range Radar (LRR) sensors, 76-77 GHz radar transceivers can be applied as an Adaptive Cruise Control (ACC) to detect the long-distance (over 100m away) objects and prevent collisions. The Short-Range Radar (SRR) sensors, which operate at 22-29 GHz and 77-81 GHz, have been developed for many other applications, such as auto-tailgate sensor, blind-spot detection, door-open warning, etc. The frequency band of 76-77 GHz and 77-81 GHz are particularly preserved for vehicular applications, including long-range detections and short-range detections. The related regulations will be introduced in Chapter 1. Many mm-Wave radar transceivers used SiGe or BiCMOS processes to achieve high-gain and high-frequency requirements. Meanwhile, as the progress of CMOS technology, more and more fully CMOS mm-Wave radar transceivers have been designed and published during past few years. A 24-GHz fully-integrated Frequency-Modulated Continuous Wave (FMCW) direct-conversion transceiver, implemented in a 55-nm low-power CMOS technology with a maximum Cut-Off frequency fT of 190 GHz in typical operating conditions and packaged in a 5-mm × 5-mm 32-lead Quad-Flat No-leads (QFN) package, is presented in this Dissertation. This single-chip transceiver uses a single 2.5-V supply while all the core circuits are powered by integrated regulators. The complex low-noise transconductor in the receiver uses a quadrature hybrid to generate quadrature signals in the receiving front-end. The analog-signal processing circuits, including high-pass filters, low-pass filters, and programmable amplifiers, have also been implemented to work with the receiver front-end circuitry. The FMCW signals are generated by an on-chip 24-GHz PLL-based Fractional-N Frequency Synthesizer. Such synthesizer is completely integrated with the transceiver and provides built-in digital frequency modulation to generate chirping signals for the down-conversion Local Oscillator (LO) and the transmitting signals. The transmitter is composed of a balanced class-AB power amplifier driven by the FMCW signals from the frequency synthesizer. In this work, a 24-GHz fully-integrated FMCW transceiver is implemented with a 55-nm CMOS technology, which cut-off frequency is about 190-GHz. The limitation of such cut-off frequency increases the difficulties in implementing high-frequency circuits, for example, the INjection-Locked Divider (INLD), Voltage-Controlled Oscillator (VCO), Low-Noise Transconductance Amplifier (LNTA), Power Amplifier (PA) and so on. The measurements and statistical results of 120 ea. chips are presented to verify the robustness of our transceiver design. The receiver maximum gain is 64 dB, and the transmitter maximum output power is 11 dBm. The total power consumption is 860 mW @ 2.5V. The die area is 7.84 mm^2.