一個利用全新可替代配置架構的高原生穩定性靜態隨機存取記憶體物理不可仿製功能電路

Abstract

本論文提出了一個利用可替代配置技術的新架構，來實現一個靜態隨機存取記憶體物理不可仿製功能電路。 為了減輕物理不可仿製功能電路中糾錯碼的使用，必須要降低物理不可仿製功能電路原生數據的位元錯誤率。然而，由於閾值電壓在製程中的不匹配為隨機分布，靜態隨機存取記憶體物理不可功能函數電路存儲單元的穩定性一直以來都不夠理想。在這裡提出的可替代配置架構中，我使用可替代的電晶體作為存儲單元內的第二熵源。新的熵源讓每個存儲單元有了二次生成穩定位元的機會，進而提升物理不可仿製功能電路的穩定性。 為了進一步提高穩定性，我們透過一個斜坡訊號作為電源供應來緩慢啟動存儲單元。在這個作品中也應用了偏置接地電壓的技巧來選擇需要屏蔽的不穩定位元。 本文提出的物理不可仿製功能電路使用180納米CMOS製程實現。在2.2V的供電下，每個位元的功耗為4370fJ。電路在20~70℃的溫度下正常運作，屏蔽暗位元後量測得到1.4*10-4的位元錯誤率。隨機性為53.1%，唯一性為45.6%。

This thesis presents a static random-access memory (SRAM) physical unclonable function (PUF) based on a new alternative configuration architecture. To lighten the use of error-correcting code (ECC) in PUF, the bit error rate (BER) of raw data from PUF must be as low as possible. SRAM PUF bit cell has an unfavorable native-BER due to the random distribution of threshold voltage mismatch. The proposed work can increase native stability by using the alternative transistors as the second entropy source in each bit cell. The new configuration brings another chance to produce stable bits. To further increase the stability, the power-up process of the PUF cell is controlled at a slow ramp rate. The VSS-biased preselection is also applied in this work to complete masking for dark bits. The proposed SRAM PUF is fabricated in a 180-nm CMOS process. The PUF core consumes 4370 fJ/bit under a 2.2-V supply. The PUF is measured functional under the temperature of 20~70℃, and the measured native-BER is 1.4 * 10-4 after masking. Randomness is 53.1%, and uniqueness is 45.6%.