通用波長路由光網路晶片架構與其在定製與容錯拓撲設計之應用

Abstract

由於有著高頻寬、低延遲、低功耗的傳輸特性，波長路由晶片上光網路是被視為一種在次世代訊號傳輸上具有前景的技術。目前在文獻上被提出的波長路由晶片上光網路拓撲設計方法大多仰賴預先設計好的架構模板。然而，這些模板在元件位置和波導交叉位置上的配置並不一定準確，導致了在估計設計成本時的誤差。 為了彌補這些缺點，在本篇論文中，我們提出一個新的波長路由晶片上光網路拓撲的通用架構。基於這個架構，我們提出了一個基於退火演算法 （Simulated Annealing, SA）的流程來設計定製拓撲。此外，我們提出兩種針對全連接連線 （full-connectivity netlist）的容錯拓撲，分別稱為輻射對稱自動修復拓撲 (Actin-STAR) 和雙軸對稱自動修復拓撲 (Zygo-STAR)。我們證明了在輻射對稱自動修復拓撲中，最大主要路徑傳輸損耗的性能界限為2.22，而在雙軸對稱自動修復拓撲中，最大備用路徑傳輸損耗的性能界限為1.11。 實驗結果顯示，與現有的拓撲網路相比，我們設計的拓撲在波長和光學環形諧振器 (Microring Resonator, MRR) 的使用量，以及在最大傳輸損耗上都能有更優異的表現。

The wavelength-routed optical network-on-chip (WRONoC) is a promising solution for advanced signal communication because of its high-bandwidth, low-latency, and power-efficient signal transmissions. Existing WRONoC topology designs rely on pre-defined network templates. However, these templates might not accurately capture the device locations and crossing occurrences, leading to inaccurate cost evaluations. To remedy this disadvantage, we present a general model for WRONoC topologies in this thesis. Based on this model, we propose a novel SA-based customized topology design flow to minimize the maximum insertion loss and the wavelength and micro-ring resonator (MRR) usage. Besides, we present two fault-tolerant topologies for full-connectivity netlists, namely the Actin-STAR and Zygo-STAR topologies. We prove that the Actin-STAR topology has a performance bound of 2.22 in the primary-path maximum insertion loss, and the Zygo-STAR topology has a performance bound of 1.11 in the backup-path one. Experimental results show that our designs significantly outperform the state-of-the-art designs in wavelength, MRR usage, and the maximum insertion loss.