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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文 | zh_TW |
| dc.contributor.advisor | Yao-Wen Chang | en |
| dc.contributor.author | 陳彥霖 | zh_TW |
| dc.contributor.author | Yan-Lin Chen | en |
| dc.date.accessioned | 2023-06-14T16:05:40Z | - |
| dc.date.available | 2025-02-02 | - |
| dc.date.copyright | 2023-06-14 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-02-04 | - |
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Lu, Topology and Layout Design Automation for Wavelength-Routed Optical Network-On-Chips. Graduate Institute of Electronics Engineering, National Taiwan University, 2021. [22] Y.-S. Lu, K.-C. Chen, Y.-L. Hsu, and Y.-W. Chang, “Thermal-aware optical-electrical routing codesign for on-chip signal communications,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1279 1284, New York, NY, USA, July 2022. [23] Y.-S. Lu, Y.-L. Chen, S.-J. Yu, and Y.-W. Chang, “Topological structure and physical layout co-design for wavelength-routed optical networks-on-chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 7, pp. 2237–2249, 2022. [24] Y.-S. Lu, S.-J. Yu, and Y.-W. Chang, “A provably good wavelength-division-multiplexing-aware clustering algorithm for on-chip optical routing,” in Proceedings of ACM/IEEE Design Automation Conference, San Francisco, CA, USA, July 2020. [25] M. C. Meyer, A. B. Ahmed, Y. Tanaka, and A. B. Abdallah, “On the design of a fault-tolerant photonic network-on-chip,” in Proceedings of IEEE International Conference on Systems, Man, and Cybernetics, pp. 821–826, Hong Kong, China, October 2015. [26] X. Tan, M. Yang, L. Zhang, Y. Jiang, and J. Yang, “On a scalable, non-blocking optical router for photonic networks-on-chip designs,” in Proceedings of Symposium on Photonics and Optoelectronics, Wuhan, China, May 2011. [27] A. Truppel, T.-M. Tseng, D. Bertozzi, J. C. Alves, and U. Schlichtmann, “PSION+: Combining logical topology and physical layout optimization for wavelength-routed ONoCs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 12, pp. 5197–5210, 2020. [28] T.-M. Tseng, A. Truppel, M. Li, M. Nikdast, and U. Schlichtmann, “Wavelength-routed optical NoCs: Design and EDA—state of the art and future directions,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Westminster, CO, USA, November 2019. [29] M. Valad Beigi and G. Memik, “MIN: A power efficient mechanism to mitigate the impact of process variations on nanophotonic networks,” in Proceedings of International Symposium on Low Power Electronics and Design, pp. 299–302, La Jolla, CA, USA, August 2014. [30] S. Werner, J. Navaridas, and M. Luj´an, “A survey on optical network-on-chip architectures,” ACM Computing Surveys, vol. 50, no. 6, 2017. [31] D. Xiang, Y. Zhang, S. Shan, and Y. Xu, “A fault-tolerant routing algorithm design for on-chip optical networks,” in Proceedings of IEEE International Symposium on Reliable Distributed Systems, Braga, Portugal, September 2013. [32] M. Xiao, T.-M. Tseng, and U. Schlichtmann, “FAST: A fast automatic sweeping topology customization method for application-specific wavelength-routed optical NoCs,” in Proceedings of ACM/IEEE Design, Automation and Test in Europe, pp. 1651–1656, Grenoble, France, February 2021. [33] Y. Xu, J. Yang, and R. Melhem, “Tolerating process variations in nanophotonic on-chip networks,” in Proceedings of International Symposium on Computer Architecture, pp. 142–152, Portland, OR, USA, June 2012. [34] Z. Zheng, M. Li, T.-M. Tseng, and U. Schlichtmann, “Light: A scalable and efficient wavelength-routed optical networks-on-chip topology,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 568–573, Tokyo, Japan, January 2021. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87514 | - |
| dc.description.abstract | 由於有著高頻寬、低延遲、低功耗的傳輸特性，波長路由晶片上光網路是被視為一種在次世代訊號傳輸上具有前景的技術。目前在文獻上被提出的波長路由晶片上光網路拓撲設計方法大多仰賴預先設計好的架構模板。然而，這些模板在元件位置和波導交叉位置上的配置並不一定準確，導致了在估計設計成本時的誤差。
為了彌補這些缺點，在本篇論文中，我們提出一個新的波長路由晶片上光網路拓撲的通用架構。基於這個架構，我們提出了一個基於退火演算法 （Simulated Annealing, SA）的流程來設計定製拓撲。此外，我們提出兩種針對全連接連線 （full-connectivity netlist）的容錯拓撲，分別稱為輻射對稱自動修復拓撲 (Actin-STAR) 和雙軸對稱自動修復拓撲 (Zygo-STAR)。我們證明了在輻射對稱自動修復拓撲中，最大主要路徑傳輸損耗的性能界限為2.22，而在雙軸對稱自動修復拓撲中，最大備用路徑傳輸損耗的性能界限為1.11。 實驗結果顯示，與現有的拓撲網路相比，我們設計的拓撲在波長和光學環形諧振器 (Microring Resonator, MRR) 的使用量，以及在最大傳輸損耗上都能有更優異的表現。 | zh_TW |
| dc.description.abstract | The wavelength-routed optical network-on-chip (WRONoC) is a promising solution for advanced signal communication because of its high-bandwidth, low-latency, and power-efficient signal transmissions. Existing WRONoC topology designs rely on pre-defined network templates. However, these templates might not accurately capture the device locations and crossing occurrences, leading to inaccurate cost evaluations.
To remedy this disadvantage, we present a general model for WRONoC topologies in this thesis. Based on this model, we propose a novel SA-based customized topology design flow to minimize the maximum insertion loss and the wavelength and micro-ring resonator (MRR) usage. Besides, we present two fault-tolerant topologies for full-connectivity netlists, namely the Actin-STAR and Zygo-STAR topologies. We prove that the Actin-STAR topology has a performance bound of 2.22 in the primary-path maximum insertion loss, and the Zygo-STAR topology has a performance bound of 1.11 in the backup-path one. Experimental results show that our designs significantly outperform the state-of-the-art designs in wavelength, MRR usage, and the maximum insertion loss. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-06-14T16:05:40Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-06-14T16:05:40Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements iii
Abstract (Chinese) iv Abstract vi List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1 Introduction to WRONoC . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Related Works Regarding WRONoC Topology Design . . . . . . . . . . . 4 1.2.1 Survey of Customized Topology Design . . . . . . . . . . . . . . . 4 1.2.2 Survey of Fault-tolerant Topology Design . . . . . . . . . . . . . . 7 1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chapter 2. Preliminaries 13 2.1 WRONoC Design Objectives . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chapter 3. Proposed Topology Model 15 3.1 Terminologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Topology Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter 4. Our Proposed Algorithm 19 4.1 Proposed Method for Customized Topology Design . . . . . . . . . . . . 19 4.1.1 Algorithm Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1.2 Topology Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1.3 Critical Path-aware SA Optimization . . . . . . . . . . . . . . . . 24 4.1.4 Wavelength Assignment . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 Proposed Method for Fault-tolerant Topology Design . . . . . . . . . . . 28 4.2.1 STAR ONoCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.2 Performance Bound of STAR ONoCs . . . . . . . . . . . . . . . . 33 Chapter 5. Experimental Results 36 5.1 Evaluation of Our Method for Customized Topology Design . . . . . . . . 36 5.1.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.2 Comparison with the State-of-the-art Customized Topology Generation Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.1.3 Evaluation of the Critical Path-aware Perturbation . . . . . . . . . 39 5.2 Evaluation of Our Method for Fault-tolerant Topology Design . . . . . . 41 5.2.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2.2 Comparison with the State-of-the-art Fault-tolerant Topology Generation Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Chapter 6. Conclusions and Future Work 44 6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2.1 Node Location-aware WRONoC Topology Design . . . . . . . . . . 45 6.2.2 WRONoC Physical Design with Movable Nodes . . . . . . . . . . . 46 6.2.3 Fault-tolerant Topology Design for Customized Netlists . . . . . . 47 Bibliography 48 Publication List 54 | - |
| dc.language.iso | en | - |
| dc.subject | 網路拓撲 | zh_TW |
| dc.subject | 容錯拓撲 | zh_TW |
| dc.subject | 定製拓撲 | zh_TW |
| dc.subject | 晶片上光網路 | zh_TW |
| dc.subject | 波長路由 | zh_TW |
| dc.subject | Customized Topology | en |
| dc.subject | Fault-tolerant Topology | en |
| dc.subject | Optical Network-on-Chip | en |
| dc.subject | Network Topology | en |
| dc.subject | Wavelength Routing | en |
| dc.title | 通用波長路由光網路晶片架構與其在定製與容錯拓撲設計之應用 | zh_TW |
| dc.title | A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Customized and Fault-Tolerant Topology Designs | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳宏明;江蕙如;方劭云;黃婷婷 | zh_TW |
| dc.contributor.oralexamcommittee | Hung-Ming Chen;Hui-Ru Jiang;Shao-Yun Fang;Ting-Ting Hwang | en |
| dc.subject.keyword | 網路拓撲,定製拓撲,容錯拓撲,晶片上光網路,波長路由, | zh_TW |
| dc.subject.keyword | Network Topology,Customized Topology,Fault-tolerant Topology,Optical Network-on-Chip,Wavelength Routing, | en |
| dc.relation.page | 54 | - |
| dc.identifier.doi | 10.6342/NTU202300255 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2023-02-08 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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