二維材料堆疊結構在電晶體及記憶體之應用研究

Abstract

本論文研究目標著重在二維材料的成長及元件製作分析、異質結構 (Hetero-structure) 與平面式閘極電晶體 (In-plane Gate Transistor, IPGT) 應用，主要研究材料為石墨烯 (Graphene) 、過渡金屬二硫化物的二硫化鉬(MoS2) 以及二硫化鎢 (WS2)。傳統化學氣相沉積法成長二維材料，需將過渡金屬和硫族元素的兩種前驅物同時放置於高溫爐管中反應，化學反應極其複雜，此外由於二維材料成長溫度相當高，異質結構薄膜製備不易，我們利用原子層沉積、熱蒸鍍、射頻濺鍍等方式提供過渡金屬氧化物薄膜，結合高溫爐管的硫化過程，我們成功製備出大面積石墨烯和二硫化鉬、二硫化鎢薄膜。我們在研究過程中發現由於缺乏斷鍵，二維材料表面不利於原子層沉積之前驅物分布，藉由調整前驅物靜置時間在二維材料表面形成成核點有利於原子層沉積，利用此方式在二硫化鉬表面成長5 nm氧化鋁做為間隔層並轉印同質材料MoS2 以增強螢光光譜發光強度或是異質材料WS2形成雙波段螢光發光結構。我們並將石墨烯直接成長於藍寶石基板上，再使用熱蒸鍍取代射頻濺鍍提供過渡金屬氧化物薄膜來成長過渡金屬二硫化物，避免濺鍍時氬離子轟擊底層材料造成破壞，使用此成長方式製備成二硫化鉬/石墨烯電晶體元件。以二硫化鉬做為表面鈍化層則可提升石墨烯電晶體之電流和載子遷移率。若使用原子層蝕刻技術將上層二硫化鉬孤立做為電荷儲存層，此異質結構之元件便會出現遲滯現象可做為記憶體元件應用。為了探討電荷儲存於二硫化鉬之現象，我們以三層二硫化鉬並使用原子層蝕刻技術將電極下方二硫化鉬蝕刻使通道中的二硫化鉬孤立做為電荷儲存層，我們發現隨著孤立層數增加其遲滯曲線亦會增加。此外為了避免氧化物與通道接觸會使得石墨稀上閘極電晶體的特性下降，我們藉由電子束微影製作出石墨烯平面式閘極電晶體，此元件無須使用氧化物介電層便可對石墨烯通道的電流進行調制並大幅提升石墨烯電晶體的元件特性。

The thesis is focused on the fabrication of 2-D materials, and their hetero-structures for device applications. The main research materials are graphene and transition metal disulfides, such as MoS2 and WS2. By using the conventional chemical vapor deposition, the growth of 2-D materials requires two precursors of transition metals and chalcogenides. Considering the thin-body nature of 2-D materials, it is difficult to achieve precise control over the growth parameters. On the other hand, high growth temperatures are usually required for 2-D material growth, which will make it difficult to establish epitaxially grown 2-D material hetero-structures. Therefore, we have adopted atomic layer deposition (ALD), thermal evaporation, and radio frequency sputtering (RF sputtering) to provide transition metal oxide films. Combined with the sulfurization procedure in a hot furnace, we have successfully demonstrated large-area graphene, molybdenum disulfide and tungsten disulfide growth. Since there are no dangling bonds, direct oxide growth by using ALD is difficult on 2-D material surfaces. We have demonstrated that a thin 5 nm Al2O3 dielectric layer can be grown on the MoS2 surface by using ALD with an additional precursor soaking time. With the thin oxide separation layer between two mono-layer 2-D materials, luminescence enhancement is observed by transferring a mono-layer MoS2 film onto the sample, while dual color emission can be observed by transferring mono-layer WS2. We have also demonstrated that layer-number-controllable MoS2 films can be grown on graphene surfaces by sulfurizing pre-deposited MoO3 films by using the thermal evaporator. With no damages introduced during the growth procedure, significant device performance enhancement is observed for the top-gate graphene transistors with the MoS2 passivation layer. By using the atomic layer etching (ALE) procedure to isolate the topmost MoS2 layer from the graphene channel, a memory architecture based on the MoS2/graphene hetero-structure is proposed. With the semiconducting 2-D material (MoS2) as the charge separation layer and the conductive counterpart (graphene) as the channel layer, a top-gate transistor can be operated as a memory device. The long retention times and increasing current ratios between “1” and “0” states with increasing isolated MoS2 layer numbers have revealed the potential of 2-D materials for memory device applications. The same concept is also applied to multi-layer MoS2 with the isolated MoS2 layers as the charge storage layer and the underneath MoS2 layers as the channel. On the other hand, by using the electron beam lithography, the in-plane gate transistor architecture provides an alternate approach for the fabrication of 2-D transistors with reduced interfaces with other materials and the channel is modulated by electric field laterally.