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標題: | 112Gb/s 四階脈衝振幅調變電流模態接受器與32Gb/s 不歸零電壓模態接受器 112Gb/s PAM4 Current-Mode Receiver and 32Gb/s NRZ Voltage-Mode Receiver |
作者: | Chang-Yi Jen 任常誼 |
指導教授: | 陳中平(Chung-Ping Chen) |
共同指導教授: | 彭朋瑞(Pen-Jui Peng) |
關鍵字: | 可變增益放大器,連續時間等化器,前饋式等化器,決策反饋等化器, variable gain amplifier,continuous time linear equalizer,feed-forward equalizer,decision feedback equalizer, |
出版年 : | 2022 |
學位: | 碩士 |
摘要: | 本論文著重在兩個序列化/解序列化應用之電路設計,特別在於接受器端做了兩種不同製成不同速度與不同需求下的電路設計之晶片,最後透過晶片下線後進行量測與功能驗證,以此加以證明電路設計之完整性與功能有達到需求並加以改善提身品質。 第一個電路在40nm CMOS 下設計112-Gb/s PAM4 接受器的類比前端電路以及時脈前端電路。由於我們的目標在於接受器端的訊號輸入可以通過一個較大通道損失高達位於波特率下達到-20dB的通道來作補償。此時前端電路的可變增益放大器、連續時間等化器格外重要,除了要大大補償訊號以符合通道在不同速率下損失的增益,還需要顧及PAM4訊號在各級電路下保持著訊號的線性度之完整。另外時脈在接受器中也扮演著重要的角色,由於我們用了取樣與維持電路,故時脈的工作週期與相位關係是本研究要顧及的一大關鍵。 第二個電路在12nm CMOS 下設計32-Gb/s NRZ 接受器的前饋式等化器與決策反饋等化器。這邊設計與以往不同是我們加入了前饋式等化器來補償決策反饋等化器不能補到的前標訊號。另外決策反饋等化器我們還加入了滑動式標記的功能來補償位因為反射的後標訊號。 This paper focuses on the circuit design of two SerDes applications, especially on the receiver side, to make two different chips for circuit design with different speeds and different requirements, and finally, through the chip off-line to measure and functional verification is used to prove that the integrity and function of the circuit design meet the requirements and improve the quality. The first circuit designs the analog front-end and clock front-end circuits of a 112-Gb/s PAM4 receiver in 40nm CMOS. Since our goal is that a channel can compensate the signal input at the receiver with a more extensive channel loss up to -20dB at the baud rate, at this time, the variable gain amplifier and continuous time equalizer of the front-end circuit is vital. In addition to significantly compensating the signal to meet the gain loss of the channel at different rates, it is also necessary to consider the PAM4 signal to maintain the linearity of the signal at all stages of circuits of completeness. In addition, the clock also plays an essential role in the receiver. Since we use the sample and hold circuit, the clock's duty cycle and phase relationship are crucial factors to be considered in this study. The second circuit designs feed forward equalizer and decision feedback equalizer for a 32-Gb/s NRZ receiver in 12nm CMOS. The difference in the design here is that we have added a feed-forward equalizer to compensate for the pre-cursor signal that the decision feedback equalizer cannot make up. In addition to the decision feedback equalizer, we added a sliding tap function to compensate for the reflected post cursor signal. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84556 |
DOI: | 10.6342/NTU202203196 |
全文授權: | 同意授權(限校園內公開) |
電子全文公開日期: | 2022-09-23 |
顯示於系所單位: | 電子工程學研究所 |
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