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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Chang-Yi Jen | en |
dc.contributor.author | 任常誼 | zh_TW |
dc.date.accessioned | 2023-03-19T22:15:31Z | - |
dc.date.copyright | 2022-09-23 | |
dc.date.issued | 2022 | |
dc.date.submitted | 2022-09-21 | |
dc.identifier.citation | [1] T. Shibasaki et al., “A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2014, pp. 1–2. [2] T. Shibasaki, et al., “A 56Gb/s NRZ electrical 247mW/lane serial link transceiver in 28nm CMOS”, ISSCC, pp. 64-65, Feb. 2016. [3] P.A. Francese, et al., “A 50Gb/s 1.6pJ/b RX data-path with quarter-rate 3-tap speculative DFE”, IEEE Symp. VLSI Circuits, pp. 267-268, June 2018. [4] S. Parikh, et al., “A 32Gb/s Wireline Receiver with a Low-Frequency Equalizer, CTLE and 2-Tap DFE in 28nm CMOS,” ISSCC Dig. Tech. Papers, pp. 28–29, Feb. 2013. [5] K. K. Parhi, “Design of Multigigabit Multiplexer-Loop-Based Decision Feedback Equalizers,” IEEE Trans. on VLSI Systems, vol. 13, no. 4, pp 489–493, Apr. 2005. [6] D. Yoo, et al, 'A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS,' IEEE International Solid- State Circuits Conference - (ISSCC), pp. 126-128, Feb 2019. [7] V. Stojanovic, et al., 'Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver,' IEEE Symp. VLSI Circuits, pp. 348-351, June 2004. [8] A. Cevrero et al., “29.1 A 64 Gb/s 1.4 pJ/b NRZ optical-receiver datapath in 14 nm CMOS FinFET,” in IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 482–483. [9] H. Miyaoka et al., “A 28-Gb/s 4.5-pJ/bit Transceiver With 1-Tap Decision Feedback Equalizer in 28-nm CMOS,” Asian Solid-State Circuits Conf., pp. 245-248, Nov. 2015. [10] E. Depaoli, et al., 'A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR Transceiver in 28nm FDSOI CMOS,' ISSCC, pp. 110-112, Feb. 2018. [11] E. Depaoli et al., 'A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS,' in IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 6-17, Jan. 2019. [12] M. Harwood et al., “A 225mW 28Gb/s SerDes in 40nm CMOS With 13dB of Analog Equalization for 100GBASE-LR4 and Optical Transport Lane 4.4 Applications,” ISSCC Dig. Tech. Papers, pp. 326-327, Feb. 2012. [13] D. Cui, et al., “A Dual 23Gb/s CMOS Transmitter/Receiver Chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK Optical Transmission,” in ISSCC Dig. Tech. Papers, Feb. 2012, pp. 330-331. [14] M. Jeeradit, et al., “Characterizing Sampling Aperture of Clocked Comparators,” IEEE Symposium on VLSI Circuits, Aug. 2008. [15] Osama Ellhadidy, et al., “A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR Tap DFE Receiver in 65-nm CMOS,” IEEE Symposium on VLSI Circuits, Sep. 2008. [16] Ashkan Roshan-Zamir, et al., “A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS,” in IEEE Journal of Solid-State Circuits, Sep. 2017. [17] Ashkan Roshan-Zamir, et al., “A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS,” in IEEE Journal of Solid-State Circuits, MAR. 2019. [18] Hao Li, et al., “A 100Gb/s -8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE, and Direct-Feedback DFE in 29nm CMOS,” in IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, Feb. 2021 [19] Freeman Zhong, “A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS,” in IEEE Journal of Solid-State Circuits, DEC. 2011. [20] Bo Zhang, et al., “A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS,” in IEEE Journal of Solid-State Circuits, DEC. 2015. [21] Hiroshi Kimura, et al., “A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS,” in IEEE Journal of Solid-State Circuits, DEC. 2014. [22] James Bailey, et al., “A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receive,” in IEEE Journal of Solid-State Circuits, 2022. [23] Alessandro Cevrero, et al., “A 100Gb/s 1.1pj/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14 nm CMOS FinFET,” in IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, Feb. 2019 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84556 | - |
dc.description.abstract | 本論文著重在兩個序列化/解序列化應用之電路設計,特別在於接受器端做了兩種不同製成不同速度與不同需求下的電路設計之晶片,最後透過晶片下線後進行量測與功能驗證,以此加以證明電路設計之完整性與功能有達到需求並加以改善提身品質。 第一個電路在40nm CMOS 下設計112-Gb/s PAM4 接受器的類比前端電路以及時脈前端電路。由於我們的目標在於接受器端的訊號輸入可以通過一個較大通道損失高達位於波特率下達到-20dB的通道來作補償。此時前端電路的可變增益放大器、連續時間等化器格外重要,除了要大大補償訊號以符合通道在不同速率下損失的增益,還需要顧及PAM4訊號在各級電路下保持著訊號的線性度之完整。另外時脈在接受器中也扮演著重要的角色,由於我們用了取樣與維持電路,故時脈的工作週期與相位關係是本研究要顧及的一大關鍵。 第二個電路在12nm CMOS 下設計32-Gb/s NRZ 接受器的前饋式等化器與決策反饋等化器。這邊設計與以往不同是我們加入了前饋式等化器來補償決策反饋等化器不能補到的前標訊號。另外決策反饋等化器我們還加入了滑動式標記的功能來補償位因為反射的後標訊號。 | zh_TW |
dc.description.abstract | This paper focuses on the circuit design of two SerDes applications, especially on the receiver side, to make two different chips for circuit design with different speeds and different requirements, and finally, through the chip off-line to measure and functional verification is used to prove that the integrity and function of the circuit design meet the requirements and improve the quality. The first circuit designs the analog front-end and clock front-end circuits of a 112-Gb/s PAM4 receiver in 40nm CMOS. Since our goal is that a channel can compensate the signal input at the receiver with a more extensive channel loss up to -20dB at the baud rate, at this time, the variable gain amplifier and continuous time equalizer of the front-end circuit is vital. In addition to significantly compensating the signal to meet the gain loss of the channel at different rates, it is also necessary to consider the PAM4 signal to maintain the linearity of the signal at all stages of circuits of completeness. In addition, the clock also plays an essential role in the receiver. Since we use the sample and hold circuit, the clock's duty cycle and phase relationship are crucial factors to be considered in this study. The second circuit designs feed forward equalizer and decision feedback equalizer for a 32-Gb/s NRZ receiver in 12nm CMOS. The difference in the design here is that we have added a feed-forward equalizer to compensate for the pre-cursor signal that the decision feedback equalizer cannot make up. In addition to the decision feedback equalizer, we added a sliding tap function to compensate for the reflected post cursor signal. | en |
dc.description.provenance | Made available in DSpace on 2023-03-19T22:15:31Z (GMT). No. of bitstreams: 1 U0001-0609202216050400.pdf: 16391855 bytes, checksum: 4501d998a33c7f68ec161d2556282494 (MD5) Previous issue date: 2022 | en |
dc.description.tableofcontents | 中文摘要 i ABSTRACT ii CONTENTS iii LIST OF FIGURES v LIST OF TABLES viii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 2 Chapter 2 Theory 3 2.1 SerDes Introduction 3 2.2 PCI Express 5 2.3 Inter Symbol Interference 7 2.4 NRZ vs. PAM4 10 Chapter 3 Design of 112-Gb/s PAM4-RX 13 3.1 Architecture and Building Blocks 13 3.2 Analog Front End 14 3.2.1 Variable Gain Amplifier 14 3.2.2 Low-Frequency Equalizer 16 3.2.3 Continuous Time Linear Equalizer 18 3.3 14GHz Clock Path 22 3.3.1 Polyphase Filter 22 3.3.2 Phase Interpolator 25 3.3.3 Clock Correction Circuit (DCC & QEC) 28 3.3.4 Clock Calibration 33 Chapter 4 Design of 32-Gb/s NRZ-RX 36 4.1 Architecture and Building Blocks 36 4.2 Equalizer 37 4.2.1 Receiver Feed Forward Equalizer 37 4.2.2 Decision Feedback Equalizer Summer 41 4.2.3 Slicer Summer 45 4.2.4 Sliding Tap Decision Feedback Equalizer 47 4.2.5 Decision Feedback Equalizer Adaptation 51 4.3 Alignment and 1:4 Demultiplexer 52 4.4 Conclusion of 32-Gb/s NRZ-RX 53 Chapter 5 Measurement Results 56 5.1 Measurement Setup 56 5.2 Measurement Results 59 Chapter 6 Conclusion 63 REFERENCE 64 | |
dc.language.iso | en | |
dc.title | 112Gb/s 四階脈衝振幅調變電流模態接受器與32Gb/s 不歸零電壓模態接受器 | zh_TW |
dc.title | 112Gb/s PAM4 Current-Mode Receiver and 32Gb/s NRZ Voltage-Mode Receiver | en |
dc.type | Thesis | |
dc.date.schoolyear | 110-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 彭朋瑞(Pen-Jui Peng) | |
dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin) | |
dc.subject.keyword | 可變增益放大器,連續時間等化器,前饋式等化器,決策反饋等化器, | zh_TW |
dc.subject.keyword | variable gain amplifier,continuous time linear equalizer,feed-forward equalizer,decision feedback equalizer, | en |
dc.relation.page | 67 | |
dc.identifier.doi | 10.6342/NTU202203196 | |
dc.rights.note | 同意授權(限校園內公開) | |
dc.date.accepted | 2022-09-22 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
dc.date.embargo-lift | 2022-09-23 | - |
顯示於系所單位: | 電子工程學研究所 |
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