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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84398| Title: | 56-Gb/s 不歸零碼接收器 56-Gb/s NRZ Receiver |
| Authors: | Chung-Yun Tsai 蔡仲耘 |
| Advisor: | 陳中平(Chung-Ping Chen) |
| Co-Advisor: | 彭朋瑞(Pen-Jui Peng) |
| Keyword: | 可變增益放大器,連續時間等化器,決策反饋等化器,波特率相位偵測器,相位內插器,全數位式時脈資料恢復器, variable gain amplifier,low frequency equalizer,continuous time linear equalizer,decision feedback equalizer,baud rate phase detector,all digital clock and data recovery, |
| Publication Year : | 2022 |
| Degree: | 碩士 |
| Abstract: | 本論文旨在40nm CMOS中演示使用波特率時脈資料恢復電路的56-Gb/s NRZ接收器。 此架構可以共享資料決策和相位檢測的比較器，可以大幅度地減少比較器的數量並且降低晶片整體的功耗，內部電路包括可變增益放大器、連續時間等化器、一抽頭決斷反饋等化器、基於相位內插器之全數位時脈資料恢復電路。 The objective of this thesis is to demonstrate the application of baud-rate clock and data recovery in a 56-Gb/s NRZ receiver with TSMC standard digital 40nm CMOS technology. This architecture can share data decision and phase detection comparators, greatly reduce the number of comparators, power consumption, the internal circuit , including variable gain amplifier, continuous time equalizer, one-tap decision feedback equalizer, and all digital clock data recovery circuit based on phase interpolator. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84398 |
| DOI: | 10.6342/NTU202200611 |
| Fulltext Rights: | 同意授權(限校園內公開) |
| metadata.dc.date.embargo-lift: | 2022-03-07 |
| Appears in Collections: | 電子工程學研究所 |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| U0001-0203202213293900.pdf Access limited in NTU ip range | 2.55 MB | Adobe PDF |
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