使用自動頻段選擇器之7~10.5-Gb/s半速率線性時脈資料還原電路

Abstract

本論文提出了一種7~10.5-Gb/s的無參考時鐘時脈資料回復電路。 通過使用所提出的頻率遞減電路和自動頻段選擇器，線性半速率相位偵測器擴展了頻率捕獲範圍。 此外頻率遞減電路還動態地控制電荷泵的電流，以縮短頻率捕獲時間。 此時脈資料回復電路採用40奈米CMOS工藝製造，有效面積為0.102 mm^2。 時脈資料回復電路的總功率為39.6mW。 對於2^15-1的10.5-Gb/s偽隨機位元序列，在反序列化之回復數據速率為656.25Mbps下的測量均方根抖動為5ps。 量測得的高頻抖動容忍度等於0.26 UIPP，而回復資料的誤碼率小於10^−12。

In this thesis, a 7~10.5-Gb/s reference-less clock and data recovery (CDR) circuit is presented. By using the proposed frequency decremental circuit (FDC) and the automatic band selector, the frequency capture ranges of a CDR using a linear phase detector is extended. The FDC also dynamically controls the current of the charge pump to shorten the frequency acquisition time. This CDR circuit is fabricated in the 40-nm CMOS process and its active area is 0.102 mm^2. The power of the CDR circuit is 39.6mW. For a 10.5-Gb/s PRBS of 2^15−1, the measured root-mean-square jitter of the deserialized-by-16 retimed data at 656.25Mbps is 5ps. The measured high-frequency jitter tolerance is 0.26 UIPP while the bit error rate is less than 10^−12.