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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84362完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Yi-En Hsu | en |
| dc.contributor.author | 徐溢恩 | zh_TW |
| dc.date.accessioned | 2023-03-19T22:09:26Z | - |
| dc.date.copyright | 2022-07-05 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-05-03 | |
| dc.identifier.citation | S. Byun et al., “A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector,” IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2566-2576, Nov. 2006. R. Reutemann et al., “A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2850-2860, Dec. 2010. S. H. Chu et al., “A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process,” IEEE J. Solid-State Circuits, vol. 51, no. 11, pp. 2603-2612, Nov. 2015. Z. Hong et al., “A 3.12 pJ/bit, 19–27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2625-2634, Nov. 2015. D. Dalton et al., “A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2713-2725, Dec. 2005. R. J. Yang et al., “A 155.52 Mbps-3.125 Gbps continuous-rate clock and data recovery circuit,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1380-1390, June 2006. S. Byun, “A 400 Mb/s~2.5 Gb/s reference-less CDR IC using intrinsic frequency detection capability of half-rate linear phase detector,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 63, no. 10, pp. 1592-1604, Oct. 2016. G. Shu et al., “A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition,” IEEE J. Solid-State Circuits, vol. 51, no. 2, pp. 428-439, Feb. 2016. C. Z. Yu et al., “A 6.5-12.5-Gb/s half-rate single-loop all-digital reference-less CDR in 28-nm CMOS,” IEEE J. Solid-State Circuits, vol. 55, no. 10, pp. 2831-2841, July 2020. F. T. Chen et al., “A 10-Gb/s low jitter single-loop clock and data recovery circuit with rotational phase frequency detector,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 11, pp. 3278-3287, Nov. 2014. K. Park et al., “A 4-20-Gb/s 1.87-pJ/b continuous-rate digital CDR circuit with unlimited frequency acquisition capability in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 56, no. 5, pp. 1597-1607, May 2021. J. Cao et al., “OC-192 transmitter and receiver in standard 0.18-m CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1768–1780, Dec. 2002. Y. C. Huang, P. Y. Wang, and S. I. Liu, “An all-digital jitter tolerance measurement technique for CDR circuits,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 3, pp. 148-152, Dec. 2012. L. Heller et al., “Cascode voltage switch logic: A differential CMOS logic family,” in IEEE ISSCC Dig. Tech. Papers, pp. 16-17, Feb. 1984. B. Nikolic et al., “Improved sense-amplifier-based flip-flop: design and measurements,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876-884, June 2000. P. K. Hanumolu et al., “A Wide-Tracking Range Clock and Data Recovery Circuit,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 425-439, Feb. 2008. B. Razavi, Design of Integrated Circuits for Optical Communications, 2th ed. Hoboken, NJ: Wiley, 2012. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84362 | - |
| dc.description.abstract | 本論文提出了一種7~10.5-Gb/s的無參考時鐘時脈資料回復電路。 通過使用所提出的頻率遞減電路和自動頻段選擇器，線性半速率相位偵測器擴展了頻率捕獲範圍。 此外頻率遞減電路還動態地控制電荷泵的電流，以縮短頻率捕獲時間。 此時脈資料回復電路採用40奈米CMOS工藝製造，有效面積為0.102 mm^2。 時脈資料回復電路的總功率為39.6mW。 對於2^15-1的10.5-Gb/s偽隨機位元序列，在反序列化之回復數據速率為656.25Mbps下的測量均方根抖動為5ps。 量測得的高頻抖動容忍度等於0.26 UIPP，而回復資料的誤碼率小於10^−12。 | zh_TW |
| dc.description.abstract | In this thesis, a 7~10.5-Gb/s reference-less clock and data recovery (CDR) circuit is presented. By using the proposed frequency decremental circuit (FDC) and the automatic band selector, the frequency capture ranges of a CDR using a linear phase detector is extended. The FDC also dynamically controls the current of the charge pump to shorten the frequency acquisition time. This CDR circuit is fabricated in the 40-nm CMOS process and its active area is 0.102 mm^2. The power of the CDR circuit is 39.6mW. For a 10.5-Gb/s PRBS of 2^15−1, the measured root-mean-square jitter of the deserialized-by-16 retimed data at 656.25Mbps is 5ps. The measured high-frequency jitter tolerance is 0.26 UIPP while the bit error rate is less than 10^−12. | en |
| dc.description.provenance | Made available in DSpace on 2023-03-19T22:09:26Z (GMT). No. of bitstreams: 1 U0001-1204202220451400.pdf: 3919831 bytes, checksum: 1decea5c6767121c33779e292e9ed3bc (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | 1. Introduction 1 1.1 Overview 1 1.2 Wireline Communication 1 1.3 Frequency Acquisition of Clock and Data Recovery 2 1.3.1 Reference CDR 3 1.3.2 Reference-less CDR 3 1.4 Thesis Organization 5 2. A 7~10.5-Gb/s Reference-Less Linear Half-rate CDR Circuit Using Automatic Band Selector 7 2.1 Motivation 7 2.2 Circuit Description 8 2.2.1 Half-rate Linear PD with Frequency Decremental Circuit 9 2.2.2 Automatic Band Selector 12 2.2.3 VCO 18 2.2.4 Charge Pump 18 2.2.5 1:8 Demultiplexer 19 2.2.6 Parameters of CDR Circuit 20 2.3 Simulation Results 21 3. Measurement Setup and Experimental Results 31 3.1 Die Photo and Power Breakdown 31 3.2 Measurement Setup 32 3.3 Experiment Results 33 4. Conclusion and Future Work 39 4.1 Conclusion 39 4.2 Future Work 40 Bibliography 41 | |
| dc.language.iso | en | |
| dc.subject | 頻率捕獲 | zh_TW |
| dc.subject | 時脈資料回復電路 | zh_TW |
| dc.subject | Frequency acquisition | en |
| dc.subject | Clock and data recovery circuit | en |
| dc.title | 使用自動頻段選擇器之7~10.5-Gb/s半速率線性時脈資料還原電路 | zh_TW |
| dc.title | A 7~10.5-Gb/s Reference-Less Linear Half-rate CDR Circuit Using Automatic Band Selector | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 110-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 鄭國興(Kuo-Hsing Cheng),陳巍仁(Wei-Zen Chen),楊清淵(Ching-Yuan Yang) | |
| dc.subject.keyword | 時脈資料回復電路,頻率捕獲, | zh_TW |
| dc.subject.keyword | Clock and data recovery circuit,Frequency acquisition, | en |
| dc.relation.page | 44 | |
| dc.identifier.doi | 10.6342/NTU202200690 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2022-05-04 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2022-07-05 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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