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DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 郭斯彥(Sy-Yen Kuo) | |
dc.contributor.author | Ching-Hsiang Chang | en |
dc.contributor.author | 張景翔 | zh_TW |
dc.date.accessioned | 2021-05-20T00:52:36Z | - |
dc.date.available | 2020-08-04 | |
dc.date.available | 2021-05-20T00:52:36Z | - |
dc.date.copyright | 2020-08-04 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-07-31 | |
dc.identifier.citation | [1] M. Fyrbiak, S. Wallat, P. Swierczynski, M. Hoffmann, S. Hoppach, M. Wilhelm, T. Weidlich, R. Tessier, and C. Paar, “Hal — the missing piece of the puzzle for hardware reverse engineering, trojan detection and insertion,” IEEE Transactions on Dependable and Secure Computing, vol. 16, no. 3, pp. 498–510, 2019. [2] X. Zhang and M. Tehranipoor, “Case study: Detecting hardware trojans in third party digital ip cores,” in 2011 IEEE International Symposium on HardwareOriented Security and Trust, pp. 67–70, 2011. [3] M. Fyrbiak, S. Strauss, C. Kison, S. Wallat, M. Elson, N. Rummel, and C. Paar “Hardware reverse engineering: Overview and open challenges,” 2017 IEEE 2nd International Verification and Security Workshop (IVSW), pp. 88–94, 2017. [4] M. C. Hansen, H. Yalcin, and J. P. Hayes, “Unveiling the iscas-85 benchmarks: a case study in reverse engineering,” IEEE Design Test of Computers, vol. 16, no. 3, pp. 72–80, 1999. [5] P. Subramanyan, N. Tsiskaridze, K. Pasricha, D. Reisman, A. Susnea, and S. Malik, “Reverse engineering digital circuits using functional analysis,” in Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’13, (San Jose, CA, USA), pp. 1277–1280, EDA Consortium, 2013. [6] P. Subramanyan, N. Tsiskaridze, W. Li, A. Gascon, W. Tan, A. Tiwari, N. Shankar, S. A. Seshia, and S. Malik, “Reverse engineering digital circuits using structural and functional analyses,” IEEE Transactions on Emerging Topics in Computing, vol. 2, pp. 63–80, jan 2014. [7] W. Li, A. Gascon, P. Subramanyan, W. Tan, A. Tiwari, S. Malik, N. Shankar, and S. A. Seshia, “Wordrev: Finding word-level structures in a sea of bit-level gates,” in 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), (Los Alamitos, CA, USA), pp. 67–74, IEEE Computer Society, jun 2013. [8] T. Meade, S. Zhang, and Y. Jin, “Netlist reverse engineering for high-level functionality reconstruction,” in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 655–660, 2016. [9] Y. Shi, C. W. Ting, B. Gwee, and Y. Ren, “A highly efficient method for extracting fsms from flattened gate-level netlist,” in Proceedings of 2010 IEEE International Symposium on Circuits and Systems, pp. 2610–2613, 2010. [10] X. Wei, Y. Diao, T. Lam, and Y. Wu, “A universal macro block mapping scheme for arithmetic circuits,” in 2015 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1629–1634, 2015. [11] A. Mishchenko, S. Chatterjee, R. Jiang, and R. K. Brayton, “Fraigs: A unifying representation for logic synthesis and verification,” tech. rep., 2005. [12] R. Brayton and A. Mishchenko, “Abc: An academic industrial-strength verification tool,” in Proceedings of the 22Nd International Conference on Computer Aided Verification, CAV’10, (Berlin, Heidelberg), pp. 24–40, Springer-Verlag, 2010. [13] H. Katebi and I. L. Markov, “Large-scale boolean matching,” in 2010 Design, Automation Test in Europe Conference Exhibition (DATE 2010), (Los Alamitos, CA, USA), pp. 771–776, IEEE Computer Society, mar 2010. [14] H. Katebi, K. A. Sakallah, and I. L. Markov, “Generalized boolean symmetries through nested partition refinement,” in Proceedings of the International Conference on Computer-Aided Design, ICCAD ’13, (Piscataway, NJ, USA), pp. 763–770, IEEE Press, 2013. [15] J. Cong, C. Wu, and Y. Ding, “Cut ranking and pruning: Enabling a general and efficient fpga mapping solution,” in Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA’99, (New York, NY, USA), pp. 29–35, ACM, 1999. [16] S. Chatterjee, A. Mishchenko, and R. Brayton, “Factor cuts,” in 2006 IEEE/ACM International Conference on Computer Aided Design, pp. 143–150, Nov 2006. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8353 | - |
dc.description.abstract | 數位電路的反向工程一直以來都是用於重建電路功能性相當有力的工具。而重建電路功能性可以有以下幾種應用:其一是可以幫助我們找出惡意電路(亦稱硬體木馬) ,其二是針對某些規格書已經佚失的舊有設計,我們可以利用反向工程的工具以便釐清其功能。據我們所知,反向工程大概是這些問題唯一的解決方案。在本研究中我們提出一個可以讓使用者從平坦化的閘級網路連線表擷取出功能模組的硬體反向工程演算法,而且不需要人工介入。提出方法使用了切割枚舉方法以及布林匹配技術以辨識我們感興趣的功能塊。更明確的說,我們推廣了現有的切割枚舉方法,讓它變成一個子電路枚舉方法,然後確認該子電路是否正好是預先定義好的巨集庫的一員。實驗結果顯示我們的方法無法擴展至含有數千個邏輯單元的電路,肇因於過大的計算複雜度。 | zh_TW |
dc.description.abstract | Digital circuit reverse engineering has been a powerful tool for circuit functionality reconstruction, which can have several applications. On the one hand, understanding the circuit’s functionality helps us to find out malicious circuitry (a.k.a. hardware Torjan) inside the device under test (DUT). On the other hand, for some legacy designs whose specification is lost, we can use reverse engineering tool to clarify its functionality. To the best of our knowledge, reverse engineering (RE) is arguably the only solution to these problems. In this work we propose a hardware reverse engineering algorithm which enables a user to extract functional modules from a flattened gate-level netlist with no manual intervention. The proposed method utilizes a cut enumeration method together with Boolean matching technique to recognize functional blocks in which we are interested. More specifically, we extend the existing cut enumeration method to a subcircuit enumeration method, and then check whether the subcircuit happen to be a functional macro block of the predefined macro library. The experimental result shows that our method cannot scale up to circuits containing thousands of logic cells because the computational complexity is just quite high. | en |
dc.description.provenance | Made available in DSpace on 2021-05-20T00:52:36Z (GMT). No. of bitstreams: 1 U0001-3007202020322300.pdf: 1119361 bytes, checksum: 92f3e8aae35c9924c47f089ca304264d (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | List of Figures vi List of Tables vii Chapter 1 Introduction 1 Chapter 2 Related works 3 Chapter 3 Preliminaries 5 3.1 Cofactor 5 3.2 Boolean network 5 3.3 And-invert graph (AIG) 6 3.4 Tool ABC 6 3.5 Boolean matching 6 3.6 Cut enumeration 8 3.6.1 Cut 8 3.6.2 Cut set 8 3.6.3 Enumerative procedure 9 3.7 Subcircuit validation 9 3.7.1 Swallowed output 10 3.7.2 Unexpected output 10 3.7.3 Valid subcircuit 11 Chapter 4 AIG hash function 12 4.1 Simple AIG hash function 12 4.2 Complex AIG hash function 14 Chapter 5 Proposed method 16 5.1 Macro library 16 5.2 Macro mapping algorithm 17 5.3 Improvement 20 Chapter 6 Experimental results 23 Chapter 7 Conclusion and future works 25 Bibliography 26 | |
dc.language.iso | en | |
dc.title | 使用巨集塊映射方法於數位電路之逆向工程 | zh_TW |
dc.title | Digital Circuit Reverse Engineering Using Macro block mapping Methods | en |
dc.type | Thesis | |
dc.date.schoolyear | 108-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 顏嗣鈞(Hsu-Chun Yen),雷欽隆(Chin-Laung Lei),陳英一(Ing-Yi Chen),袁世一(Shih-Yi Yuan) | |
dc.subject.keyword | 數位電路,反向工程,自動化設計,子電路枚舉,形式驗證,硬體安全, | zh_TW |
dc.subject.keyword | digital circuits,reverse engineering,design automation,subcircuit enumeration,formal verification,hardware security, | en |
dc.relation.page | 28 | |
dc.identifier.doi | 10.6342/NTU202002126 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2020-08-02 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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U0001-3007202020322300.pdf | 1.09 MB | Adobe PDF | 檢視/開啟 |
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