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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Wei-Chen Lin | en |
| dc.contributor.author | 林韋辰 | zh_TW |
| dc.date.accessioned | 2022-11-25T05:33:58Z | - |
| dc.date.available | 2026-08-19 | |
| dc.date.copyright | 2021-11-11 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-08-19 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/82007 | - |
| dc.description.abstract | 我們提出了一種兩階段的晶片效能預測流程，其能夠避免客戶退貨，降低功率消耗，並減少產出損失。在第一階段，我們首先預測最小工作電壓的初始值;在第二階段，我們先預測每個晶片所在的箱並應用不同的防護帶。在851顆先進的7奈米手機晶片上的實驗結果顯示，所有晶片的預測最小工作電壓都大於實際的最小工作電壓，而這能夠避免客戶退貨。此外，功耗可降低2.69%。當最小工作電壓要求為1.20縮放的最小電壓時，產出損失最多可減少5.05%。與傳統流程相比，實行我們提出的流程只需要花費多一點的運行時間，流程的運行時間仍是短的，但我們可以節省每個晶片測量最小工作電壓的時間。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-25T05:33:58Z (GMT). No. of bitstreams: 1 U0001-1608202121435700.pdf: 7373437 bytes, checksum: 3f19b7a6ec566225127018e3d8f00130 (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | Acknowledgements i 摘要 iii Abstract iv Contents v List of Figures viii List of Tables x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Techniques 6 1.3 Contribution 7 1.4 Organization 8 Chapter 2 Background 9 2.1 Process variation 9 2.2 Previous work 13 2.3 Machine Learning Models 17 2.3.1 Linear Regression 17 2.3.2 Logistic Regression 18 Chapter 3 Proposed Techniques 21 3.1 Overall Flow 21 3.2 Build Vmin Prediction Model 22 3.3 Dimension Reduction 24 3.4 Build BinPrediction Model 27 3.5 Determine Guard Band 28 Chapter 4 Experimental Results 32 4.1 Experimental Setup 32 4.2 Experiment Visualization 32 4.3 Benefit of dimension reduction 35 4.4 Different number of bins 37 4.5 Power Saving 38 4.6 Yield loss reduction 39 4.7 Time Comparison 40 Chapter 5 Discussion 42 Chapter 6 Conclusion 44 References 45 | |
| dc.language.iso | en | |
| dc.subject | 多重裝箱 | zh_TW |
| dc.subject | 晶片效能預測 | zh_TW |
| dc.subject | 製程變異 | zh_TW |
| dc.subject | Chip performance prediction | en |
| dc.subject | Multiple binning | en |
| dc.subject | Process variation | en |
| dc.title | 機器學習輔助之低功率消耗的多重防護帶及最小工作電壓分級 | zh_TW |
| dc.title | ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption | en |
| dc.date.schoolyear | 109-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 江蕙如(Hsin-Tsai Liu),方家偉(Chih-Yang Tseng) | |
| dc.subject.keyword | 製程變異,晶片效能預測,多重裝箱, | zh_TW |
| dc.subject.keyword | Process variation,Chip performance prediction,Multiple binning, | en |
| dc.relation.page | 49 | |
| dc.identifier.doi | 10.6342/NTU202102410 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2021-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2026-08-19 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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