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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81676完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Wei-Ming Chen | en |
| dc.contributor.author | 陳尉銘 | zh_TW |
| dc.date.accessioned | 2022-11-24T09:25:36Z | - |
| dc.date.available | 2022-11-24T09:25:36Z | - |
| dc.date.copyright | 2021-07-23 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-06-28 | |
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Perez, 'A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation,' IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732-1742, Aug. 2007. [14] G. Shu, W.S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 150–151, Feb. 2014. [15] T. Masuda et al., “A 12 Gb/s 0.9 mW/Gb/s wide-bandwidth injection type CDR in 28 nm CMOS with reference-free frequency capture,” IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 3204–3215, Dec. 2016. [16] K. Park, W. Bae, J. Lee, J. Hwang, and D. K. Jeong, “A 6.7–11.2 Gb/s, 2.25 pJ/bit, single-loop referenceless CDR with multi-phase, oversampling PFD in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 53, no. 10, pp. 2982–2993, Oct. 2018. [17] N. Kocaman, S. Fallahi, M. Kargar, M. Khanpour, A. Nazemi, U. Singh, and A. Momtaz, “An 8.5–11.5-Gbps SONET transceiver with referenceless frequency acquisition,” IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1875-1884, Dec. 2013. [18] M. S. Jalali, A. Sheikholeslami, M. Kibune, and H. Tamura, “A reference-less single-loop half-rate binary CDR,” IEEE J. Solid-State Circuits, vol. 50, no. 9, pp. 2037–2047, Sep. 2015. [19] J. D. H. Alexander, “Clock recovery from random binary data,” Electronics Letters, vol. 11, pp. 541-542, Oct. 1975. [20] C. R. Hogge, “A self-correcting clock recovery circuit,” IEEE J. Lightwave Tech., vol. 3, pp. 1312–1314 Dec. 1985. [21] D. Kim, M. G. Ahmed, W. S. Choi, A. Elkholy and P. K. Hanumolu, 'A 12-Gb/s 10-ns turn-on time rapid ON/OFF baud-rate DFE receiver in 65-nm CMOS,' IEEE Journal of Solid-State Circuits, vol. 55, no. 8, pp. 2196-2205, Aug. 2020. [22] M. Chen, Y. Shih, C. Lin, H. Hung and J. Lee, 'A fully-integrated 40-Gb/s transceiver in 65-nm CMOS technology,' IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 627-640, March 2012. [23] T. Shibasaki, et al., “A 56-Gb/s receiver front-end with a CTLE and 1-Tap DFE in 20-nm CMOS,” in Symp. on VLSI Circuits Dig. Tech. Papers, pp. 1-2, June 2014. [24] L. Kong, Y. Chang and B. Razavi, 'An Inductorless 20-Gb/s CDR With High Jitter Tolerance,' IEEE J. Solid-State Circuits, vol. 54, no. 10, pp. 2857-2866, Oct. 2019. [25] Z. Hong, Y. Liu, and W. Chen, “A 3.12 pJ/bit, 19-27 Gbps receiver with 2-tap DFE embedded clock and data recovery,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2625–2634, Nov. 2015. [26] H. -Y. Joo et al., 'A maximum-eye-tracking CDR with biased data-level and eye slope detector for near-optimal timing adaptation,' IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 12, pp. 2708-2720, Dec. 2020. [27] J. Lee et al., “A 0.1 pJ/b/dB 1.62-to-10.8 Gb/s video interface receiver with fully adaptive equalization using un-even data level,” in Symp. on VLSI Circuits Dig. Tech. Papers, pp. C198–C199, June 2019. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81676 | - |
| dc.description.abstract | 這篇論文的主題 主要分為兩個部分，第一部分實現了一個資料傳輸率為10.4-16-Gb/s無參考頻率之鮑率數位時脈資料還原電路與1-tap決策回授等化器。提出的寬範圍鮑率頻率偵測器由粗調頻率偵測器與細調頻率偵測器所組成。此寬範圍鮑率頻率偵測器、相位偵測器與決策回授等化器共用前級高速比較器，因此無需增加任何額外高速硬體成本。除此之外，透過偵測五位元之資料序列的取樣點移動，此細調頻率偵測器可以達到穩固的頻率偵測器與相位偵測器切換。此頻率偵測器不只達到寬的頻率鎖定範圍，同時具有短的頻率追鎖時間。此架構使用台積電40奈米製程製作，核心電路面積為0.1004mm^2，操作在資料速度16Gb/s的功率消耗為39.9mW，達到的能源效率為2.49pJ/b。 第二部分實現了一個抖動容忍度增強之數位鮑率時脈資料還原電路。為了改善時脈資料還原電路的抖動容忍度，此部分提出一背景校正電路。此晶片使用台積電40奈米製程，其核心電路面積為0.1mm^2。在 通道衰減為10.31dB@10GHz與輸入資料速度為20Gb/s資料序列為PRBS2^7-1下，資料錯誤率10^-12。 透過所提出的校正電路，此電路改善量測到的高頻抖動容忍度。量測到的收斂時間小於5微秒，操作在資料速度20Gb/s的功率消耗為55.4mW，達到的能源效率為2.77pJ/b 。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-24T09:25:36Z (GMT). No. of bitstreams: 1 U0001-2706202120322400.pdf: 8815666 bytes, checksum: b99eb4383e0cec88950eb45c526a1157 (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | 1. Introduction………………………………………………………… 1 1.1 Overview…………………………………………………….. 1 1.2 Wireline Communication…...……………………………….. 1 1.3 1.3 Baud-Rate Clock and Data Recovery Circuit………….. 2 1.4 Thesis Organization…………………………………………. 3 2. A 10.4-16-Gb/s Reference-Less Baud-Rate Digital CDR with One-Tap DFE Using a Wide-range FD 5 2.1 Motivation…………………………………………………… 5 2.2 Baud-Rate FD……………………………………………….. 6 2.2.1 Overview of a Pattern-based Baud-Rate PD………… 6 2.2.2 Phasor Diagram………..……………...……………... 7 2.2.3 CFD………………………………………………….. 9 2.2.4 FFD……………....…………………………………... 14 2.2.5 FCR of the FFD….....………………………………... 16 2.3 Circuit Description................………………………………... 19 2.4 Simulation Result..................................................................... 23 2.5 Experiment Result…………………………………………… 26 3. A 20-Gb/s Jitter-Tolerance-Enhanced Baud-Rate Digital CDR Circuit with One-Tap DFE……….………………………………... 33 3.1 Motivation……………………………………….................... 33 3.2 Calibration Principle…..……………………………………... 34 3.2.1 Calibration Method….……………..……………….. 34 3.2.2 Parameter Selection of Calibration Circuit......……... 37 3.3 Circuit Description................………………………………... 38 3.3.1 Quarter-Rate CDR with One-Tap DFE…….……….. 38 3.3.2 Calibration Circuit………………………………….. 39 3.3.3 Other Building Blocks……………………………… 41 3.4 Simulation Result……………………………………………. 42 3.5 Experiment Result…………………………………………… 44 4. Conclusion and Future Work……………………………………… 49 4.1 Conclusion…………………………………………………… 50 4.2 Future Work…………………………………………………. 50 Bibliography ……………………………………………………………… 51 | |
| dc.language.iso | en | |
| dc.subject | 鮑率 | zh_TW |
| dc.subject | 頻率偵測器 | zh_TW |
| dc.subject | 抖動容忍度 | zh_TW |
| dc.subject | 等化器 | zh_TW |
| dc.subject | 時脈資料還原電路 | zh_TW |
| dc.subject | frequency detector | en |
| dc.subject | equalizer | en |
| dc.subject | clock/data recovery | en |
| dc.subject | jitter tolerance | en |
| dc.subject | baud-rate | en |
| dc.title | 使用寬範圍頻率偵測器與抖動容忍度增強技術的鮑率時脈資料還原電路 | zh_TW |
| dc.title | Baud-Rate Clock/Data Recovery Circuits with Wide-range FD and Jitter-Tolerance-Enhanced Technique | en |
| dc.date.schoolyear | 109-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成(Hsin-Tsai Liu),林宗賢(Chih-Yang Tseng),鄭國興,陳巍仁 | |
| dc.subject.keyword | 鮑率,頻率偵測器,抖動容忍度,等化器,時脈資料還原電路, | zh_TW |
| dc.subject.keyword | baud-rate,frequency detector,jitter tolerance,equalizer,clock/data recovery, | en |
| dc.relation.page | 53 | |
| dc.identifier.doi | 10.6342/NTU202101157 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2021-06-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
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