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標題: | 適用於類比與混合訊號電路系統之時間延遲電路設計與製作 The Design and Realization of Time Delay Circuitry for Analog and Mixed-Signal Systems |
作者: | Yu-Chuan Lin 林有銓 |
指導教授: | 曹恆偉(Hen-Wei Tsao) |
關鍵字: | 電壓對時間轉換器,時間數位轉換器,時間模式類比數位轉換器,眼圖觀測,多相位產生器, voltage-to-time difference converter (VTC),time-to-digital converter (TDC),time domain ADC,eye monitor,multi-phase generator, |
出版年 : | 2020 |
學位: | 博士 |
摘要: | 由於CMOS製程不斷的演進以及操作電壓越來越低的情況下,使用傳統類比電路設計方式,要製作出低功耗以及小面積的電路變得越來越具挑戰性。因此,在一些高速但解析度要求適中的類比電路中,改用在時間軸上做信號處理變得越來越廣泛。近年來,時間數位轉換器電路已經被廣泛應用在全數位式鎖相迴路以及時間模式的類比數位轉換器當中。在低電壓,低功率以及小面積的設計要求下,在時間軸上的信號處理電路在類比電路系統中佔有著極大的優勢。 在本論文中,希望發展一些時間軸上的信號轉換以及信號處理電路應用在純類比或類比數位混合電路當中。首先,我們提出一種新型高速高解析度電壓對時間差轉換器電路,用以結合快閃式時間數位轉換器來實現高速類比數位轉換器。使用0.18-μm CMOS製程,所提出的類比數位轉換器在使用1.8-V 操作電壓下,功耗為16-mW。此外,在400-MHz的取樣頻率下量測100-MHz的弦波輸入信號,其信噪失真比以及無雜散動態範圍分別為26.1 dB 以及31.5 dB。 其次,我們提出一種新型的多相位時脈輸出電路應用在晶片內部的一維眼圖觀測電路。使用65nm CMOS製程,所提出的一維眼圖觀測電路能忠實反映出接收信號眼開程度,用以協助串列接收器前端等化器作信號調適。在10 Gbps的資料傳輸速率下,使用1-V的操作電壓,量測到的功耗為1.5-mW。佈局面積僅佔 0.027mm2。 Owing to the advanced CMOS technology and downscaling supply voltage, analog circuit design in the traditional voltage or current domains is becoming more and more of a challenge for both power reduction and area minimization. Time-domain signal processing is becoming increasingly prevalent in high-speed and moderate-accuracy analog circuitries. Recently, time-to-digital converters (TDCs) have been widely used in all digital PLL and time domain ADCs. An analog-type signal has to be converted to a time mode signal first and then time mode circuit TDC convert the time mode signal to digital code. The time domain processing circuits using in analog circuitries will be greatly beneficial to a low-supply voltage, low power consumption and small area required design. In this dissertation, several time converting and processing circuits are proposed and implemented in some analog or mixed-mode circuits. First, a novel high-speed, high accuracy voltage-to-time difference converter (VTC) is presented and integrated with a flash type time-to-digital converter (TDC) to realize a high speed time-based ADC (TADC). Fabricated in a 0.18-μm CMOS technology, the proposed ADC consumes 16-mW at a 1.8-V supply voltage. Moreover, the measured signal to noise and distortion ratio and spurious-free dynamic range are 26.1 dB and 31.5 dB, respectively, at a 400-MHz sampling frequency for a 100-MHz input signal. Next, an on-chip one-dimensional eye-opening monitor (1D-EOM) with a novel multi-phase generator circuit is proposed. Fabricated in a 65nm CMOS technology, the proposed 1D-EOM circuit can faithful reflect the eye opening of the received data and assist the adaptations of equalizer in serial link receiver front-end. The EOM circuit monitors a 10 Gbps data and the power consumption is only 1.5-mW at a 1-V supply voltage. Occupied layout area is 0.027mm2. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8137 |
DOI: | 10.6342/NTU202003926 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 電子工程學研究所 |
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U0001-1808202010182300.pdf | 4.3 MB | Adobe PDF | 檢視/開啟 |
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