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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/79517完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
| dc.contributor.author | Hung-Lin Chen | en |
| dc.contributor.author | 陳鋐霖 | zh_TW |
| dc.date.accessioned | 2022-11-23T09:02:32Z | - |
| dc.date.available | 2021-11-08 | |
| dc.date.available | 2022-11-23T09:02:32Z | - |
| dc.date.copyright | 2021-11-08 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-10-01 | |
| dc.identifier.citation | [1] M. Psarakis, D. Gizopoulos, E. Sanchez and M. Sonza Reorda, 'Microprocessor Software-Based Self-Testing,' in IEEE Design Test of Computers, vol. 27, no. 3, pp. 4-19, May-June 2010. [2] P. Bernardi et al., 'On the in-field functional testing of decode units in pipelined RISC processors,' 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, pp. 299-304. [3] K. Kambe, M. Inoue and H. Fujiwara, 'Efficient template generation for instruction-based self-test of processor cores,' 13th Asian Test Symposium, 2004, pp. 152-157. [4] N. Hage, R. Gulve, M. Fujita and V. Singh, 'On Testing of Superscalar Processors in Functional Mode for Delay Faults,' 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017, pp. 397-402. [5] P. Bernardi et al., 'On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors,' 2013 14th International Workshop on Microprocessor Test and Verification, 2013, pp. 52-57. [6] T. Lu, C. Chen and K. Lee, 'Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 3, pp. 516-520, March 2011. [7] M. S. Vasudevan, S. Biswas and A. Sahu, 'RSBST: A Rapid Software-Based Self-Test Methodology for Processor Testing,' 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), 2019, pp. 112-117. [8] M. Psarakis, D. Gizopoulos, M. Hatzimihail, A. Paschalis, A. Raghunathan and S. Ravi, 'Systematic software-based self-test for pipelined processors,' 2006 43rd ACM/IEEE Design Automation Conference, 2006, pp. 393-398. [9] A. Riefert, L. Ciganda, M. Sauer, P. Bernardi, M. S. Reorda and B. Becker, 'An effective approach to automatic functional processor test generation for small-delay faults,' 2014 Design, Automation Test in Europe Conference Exhibition (DATE), 2014, pp. 1-6. [10] Y. Zhang, H. Li and X. Li, 'Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 7, pp. 1220-1233, July 2013. [11] Y. Zhang, H. Li and X. Li, 'Software-Based Self-Testing of Processors Using Expanded Instructions,' 2010 19th IEEE Asian Test Symposium, 2010, pp. 415-420. [12] C. H. -. Wen, Li-C Wang and Kwang-Ting Cheng, 'Simulation-Based Functional Test Generation for Embedded Processors,' in IEEE Transactions on Computers, vol. 55, no. 11, pp. 1335-1343, Nov. 2006. [13] B. Y. Yang, 'Automatic Pattern-to-Program Conversion Methodology for Software-Based Self-Test,' M.S. thesis, National Taiwan University, Taipei, Taiwan, 2020. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/79517 | - |
| dc.description.abstract | "近年來，軟體自我測試（Software-Based Self-Test）由於跟生命安全攸關產品和汽車電子產品的高度發展受到更多關注。在本論文中，我們找出更換前一個軟體自我測試方法[1]的待測處理器會發生什麼樣的問題以及解決辦法。從 RISC-V處理器上的實驗結果可以看到，所提出的 SBST方法可以實現 74.36%的轉換延遲錯誤覆蓋率。在這些工作期間，我們發現分支預測會對提出的模板產生了很大影響，因此針對這個問題提出了修改的模板來符合這種技術。而且，在SBST方法中使用到分支有關的操作時，我們提供了更好的定義。此外，為了提高自動化的程度，我們針對當前指令集架構(Instruction Set Architecture, ISA) 配置檔做了修改，並添加了新的配置檔。 通過這個改進的方法，人們可以較少的努力和時間將SBST方法應用在全新的處理器架構上。此外，這個省下來的時間可以針對不同的處理器技術研究對應的新模板。" | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-23T09:02:32Z (GMT). No. of bitstreams: 1 U0001-2909202103453800.pdf: 6820645 bytes, checksum: 4bf6949364c73def6360fe873cf5eba7 (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | 口試委員會審定書 # 誌謝 i 中文摘要 ii ABSTRACT iii 目錄 iv LIST OF FIGURES vi LIST OF TABLES viii Chapter 1 Introduction 1 1.1 Software-based self-test (SBST) 1 1.2 RISC-V 2 1.3 Motivation and previous work 4 1.4 Contribution 5 1.5 Organizations of the Thesis 5 Chapter 2 Preliminaries 6 2.1 Software-based test program generation of MIPS 6 2.2 RISC-V Instruction set architecture (ISA) 13 2.3 Branch prediction 14 Chapter 3 Proposed methodology 15 3.1 Modified template for branch prediction 15 3.2 Software-based test program generation of RISC-V 19 3.3 Improved methodology for processor under test (PUT) replacement 28 Chapter 4 Experiment result 29 4.1 Experiment setup 29 4.2 Fault coverage of PUT with 20 iterations 30 4.3 Reasons of low fault coverage 34 4.4 Run time analysis 35 4.5 Test program size 35 Chapter 5 Conclusion and future work 36 5.1 Conclusion 36 5.2 Future work 37 REFERENCE 38 | |
| dc.language.iso | en | |
| dc.title | 案例研究: RISC-V處理器的測試程式生成應用於軟體自我測試 | zh_TW |
| dc.title | Case Study: Test Program Generation of RISC-V Processor for Software-Based Self-Test | en |
| dc.date.schoolyear | 109-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 温宏斌(Hsin-Tsai Liu),呂學坤(Chih-Yang Tseng),李進福 | |
| dc.subject.keyword | 軟體自我測試,RISC-V,分支預測,測試樣板,轉態延遲錯誤,超大積體電路測試, | zh_TW |
| dc.subject.keyword | Software-Based Self-Test,RISC-V,Branch Prediction,Test Template,Transition Delay Fault,VLSI Testing, | en |
| dc.relation.page | 39 | |
| dc.identifier.doi | 10.6342/NTU202103446 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2021-10-01 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| U0001-2909202103453800.pdf | 6.66 MB | Adobe PDF | 檢視/開啟 |
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