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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
| dc.contributor.author | Chun-Yu Lin | en |
| dc.contributor.author | 林君豫 | zh_TW |
| dc.date.accessioned | 2022-11-23T08:56:38Z | - |
| dc.date.available | 2022-02-21 | |
| dc.date.available | 2022-11-23T08:56:38Z | - |
| dc.date.copyright | 2022-02-21 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-01-26 | |
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Plett, “A Study of Digital and Analog Automatic-Amplitude Control Circuitry for Voltage-Controlled Oscillators,” IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 352-356, Feb. 2003. E. A. Vittoz, M. G. R. Degrauwe and S. Bitz, “High-Performance Crystal Oscillator Circuits: Theory and Application,” IEEE Journal of Solid-State Circuits, vol. 23, no. 3, pp. 774-783, Jun. 1988. M. S. McCorquodale, G. A. Carichner and J. D. O'Day, “A 25-MHz Self-Referenced Solid-State Frequency Source Suitable for XO-Replacement,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 943-956, May 2009. R. L. Bunch and S. Raman, “Large-Signal Analysis of MOS Varactors in CMOS Gm LC VCOs,” IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp. 1325-1332, Aug. 2003. How Digital Power Management Improves the Performance of Bluetooth Wireless Transceivers in the IoT, accessed on May 2021 [Online]. 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S. Z. Asl et al., “A 1.55×0.85mm2 3ppm 1.0µA 32.768kHz MEMS-Based Oscillator,” in ISSCC Dig. Tech. Papers, Feb. 2014, pp. 226-227. A. Sharkia, S. Mirabbasi, and S. Shekhar, “A 0.01mm2 4.6-to-5.6GHz Sub-Sampling Type-I Frequency Synthesizer with –254dB FOM,” in ISSCC Dig. Tech. Papers, Feb. 2018, pp. 256-257. J. Sharma and H. Krishnaswamy, “A Dividerless Reference-Sampling RF PLL with -253.5dB Jitter FOM and <-67dBc Reference Spurs,” in ISSCC Dig. Tech. Papers, Feb. 2018, pp. 258-259. J. Chuang and H. Krishnaswamy, “A 0.0049mm2 2.3GHz Sub-Sampling Ring-Oscillator PLL with Time-Based Loop Filter Achieving -236.2dB Jitter-FOM,” in ISSCC Dig. Tech. Papers, Feb. 2017, pp. 328-329. Y.-C. Hunag and S.-I. Liu, “A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing,” IEEE Journal of Solid-State Circuits, vol. 48, no. 2, pp. 417-428, Feb. 2013. A. Elkholy, M. Talegaonkar, T. Anand, and P. K. Hanumolu, “A 6.75-to-8.25GHz 2.25mW 190fsrms Integrated-Jitter PVT-Insensitive Injection-Locked Clock Multiplier Using All-Digital Continuous Frequency-Tracking Loop in 65nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2015, pp. 188-189. C.-F. Liang, K.-J. Hsiao, “An Injection-Locked Ring PLL with Self-Aligned Injection Window,” in ISSCC Dig. Tech. Papers, Feb. 2011, pp. 90-91. S, Choi, S. Yoo, Y. Lim, and J. Choi, “A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector,” IEEE Journal of Solid-State Circuits, vol. 51, no. 8, pp. 1878-1888, Aug. 2016. Y. He et al., “A 673μW 1.8-to-2.5GHz Dividerless Fractional-N Digital PLL with an Inherent Frequency-Capture Capability and a Phase-Dithering Spur Mitigation for IoT Applications,” in ISSCC Dig. Tech. Papers, Feb. 2017, pp. 420-421. S. Ye, L. Jansson, and I. Galton, “A Multiple-Crystal Interface PLL With VCO Realignment to Reduce Phase Noise,” IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1795-1803, Dec. 2002. X. Gao, A. M. Klumperink, G. Socci, M. Bohsali, and B. Nauta, “Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector,” IEEE Journal of Solid-State Circuits, vol. 45, no. 9, pp. 1809-1821, Sep. 2010. J. Tao and C.-H. Heng, “A 2.2-GHz 3.2-mW DTC-free Sampling ΔΣ Fractional-N PLL with -110 dBc/Hz In-band phase noise and -246dB FoM and -83dBc Reference Spur,' IEEE Symposium on VLSI Circuits, pp. 162-163, Jun. 2019. T. Jang et al., “A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N Phase Locked-Loop Using a Phase-Interpolating Phase-to-Digital Converter,” in ISSCC Dig. Tech. Papers, Feb. 2013, pp. 254-255. A. Elkholy et al., “A 20-to-1000MHz ±14ps Peak-to-Peak Jitter Reconfigurable Multi-Output All-Digital Clock Generator Using Open-Loop Fractional Dividers in 65nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2014, pp. 272-273. S.-Y. Hung and S. Pamarti, “A 0.5-to-2.5GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation,” in ISSCC Dig. Tech. Papers, Feb. 2019, pp. 262-263. A. Santiccioli, M. Mercandelli, A. L. Lacaita, C. Samori, and S. Levantino, “A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power,” IEEE Journal of Solid-State Circuits, vol. 54, no. 11, pp. 3149-3160, Nov. 2019. A. J. Annema, B. Nauta, R. Langevelde, and H. Tuinhout, “Analog Circuits in Ultra-Deep-Submicron CMOS,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 132-143, Jan. 2005. A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider,” IEEE Journal of Solid-State Circuits, vol. 51, no. 5, pp. 1771-1784, Aug. 2016. C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/79247 | - |
| dc.description.abstract | 在系統中需要多組不同的時脈來提供給不同的模組運作。本篇論文提出一高效節能之時脈系統架構，著重在只使用單一晶體來實現兆赫茲與低功耗千赫茲輸出並降低溫度效應下所造成的頻率偏移。此架構共包含為四個作品如下所述。 本論文的第一個晶片為溫度補償晶體震盪器，實現於180奈米製程。我們使用多組受電壓控制電容來逼近一個多項次補償函數。用此方式來取代傳統複雜的補償，可以有效地節省面積與功耗。在攝氏-30度到90度的溫度範圍下可將溫度偏移由 ±12 ppm改善至 ±3.75 ppm，此晶片面積為0.282平方毫米。 本論文第二個晶片32.768千赫茲時脈產生器，實現於180奈米製程。我們提出一頻率校正系統，重複使用時脈系統內的唯一一顆兆赫茲晶體來產生千赫茲輸出並且維持整體功耗小於1微安培，在極端的溫度範圍以一兩位元溫度感測器做偏移補償。在攝氏-50度到105度的範圍內達到±20 ppm的頻率偏差，此晶片面積為0.364平方毫米。 本論文第三顆晶片為一整數倍率時脈產生器用於提供開迴路小數除頻器的輸入訊號，實現於90奈米製程。我們使用次取樣來穩定迴路使其能夠使用注入式鎖定之技術來實現高效能的時脈輸出。在晶片面積0.26平方毫米以及0.5毫瓦功耗下，產生一2.4千兆赫茲370飛秒的時脈抖動之輸出頻率。 本論文第四顆晶片為一開迴路小數除頻器，實現於90奈米製程。在此作品中我們大幅度的降低最佔功耗與面積的數位時間轉換器模組，因此能夠於0.008平方毫米的面積下產生0.625-200兆赫茲的時脈輸出並且達到300飛秒的時脈抖動以及1.5毫瓦的功耗。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-23T08:56:38Z (GMT). No. of bitstreams: 1 U0001-1701202216243200.pdf: 6312778 bytes, checksum: 6514523f66c782d438ae0bc2539e265f (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | "中文審定書 i 英文審定書 iii 謝辭 vii 摘要 ix Abstract x List of Figures xv List of Tables xxiv Chapter 1 Motivation and Introduction 1 1.1 Motivation and introduction 1 1.2 Thesis Overview 4 Chapter 2 Piecewise Polynomial Compensation TCXO 6 2.1 Motivation of TCXO 6 2.2 TCXO Prior Arts 8 2.3 Proposed Piecewise Polynomial Compensation TCXO 10 2.3.1 Operation Principle 10 2.3.2 Proposed TCXO Structure 11 2.3.3 Design Considerations 13 2.4 Circuit Implementation and Simulation Results 15 2.4.1 Crystal Oscillator 15 2.4.2 Positive Temperature Coefficient Voltage Generator 17 2.4.3 Proposed Piecewise Polynomial Varactor 21 2.5 Measurement results 26 Chapter 3 System-Clock-Assisted 32.768 kHz Clock Generator 34 3.1 Motivation and Introduction 34 3.2 32.768 kHz Clock Generator Prior Arts 35 3.3 Proposed 32.768 kHz clock generator structure 38 3.3.1 Operation Principle 38 3.3.2 Proposed System-Clock-Assisted 32.768 kHz Clock Generator 39 3.4 Circuit Implementation 44 3.4.1 Relaxation OSC 44 3.4.2 Low power kHz Fractional-N PLL 46 3.4.3 Temperature Sensor Design 48 3.4.4 Power System Design 48 3.5 System Simulation Results 51 3.6 Measurement results 53 Chapter 4 Sub-Sampling Sub-Harmonically Injection-Locked PLL 60 4.1 Motivation and Prior Arts 60 4.2 Proposed Sub-Sampling Sub-Harmonically Injection-Locked PLL 63 4.2.1 Operation Principle 63 4.2.2 Proposed Structure 65 4.2.3 Design Considerations 67 4.3 Circuit Implementation 69 4.3.1 VCO, Buffer, and Sub-Sampling Part 69 4.3.2 DTC and Pulse Generator 70 4.4 Simulation results 70 4.4.1 Block Simulation Results 70 4.4.2 System Simulation Results 73 4.5 Measurement results 76 Chapter 5 Fractional Output Divider 81 5.1 Motivation, Introduction and Prior Art 81 5.1.1 Motivation 81 5.1.2 Fractional Output Divider Introduction 83 5.1.3 Prior Art 86 5.2 Proposed Replica-DTC-Free Fractional Output Divider 88 5.2.1 Two Replica-DTC Structure 88 5.2.2 One Replica-DTC Structure 89 5.2.3 Concept of the Replica-DTC-Free Structure 90 5.2.4 Replica-DTC-Free Calibration Operation 91 5.2.5 Dual-Divider Structure 93 5.2.6 Proposed Structure 95 5.2.7 Design Considerations 96 5.3 Schematic and Simulation Results 102 5.3.1 Digital-to-Time Converter 102 5.3.2 Pulse-to-Voltage Converter 107 5.3.3 Multi-Modulus Divider 110 5.3.4 Comparator 111 5.3.5 System Simulation Results 112 5.4 Measurement results 114 Chapter 6 Conclusions 127 References 129 Publication List 134 List of Figures Fig. 1 1 Traditional Timing Architecture in (a) communication applications and (b) broadcast video applications 2 Fig. 1 2 FOD-based clock system. 3 Fig. 1 3 The clock system with low-power 32.768kHz output function. 3 Fig. 1 4 High-performance energy-efficient clock generation system. 4 Fig. 1 5 Proposed clock generation system chapter description. 5 Fig. 2 1 Temperature inaccuracy relationship. 6 Fig. 2 2 Temperature inaccuracy relationship. 7 Fig. 2 3 TCXO compensation operation. 8 Fig. 2 4 (a) TCXO with a polynomial compensation via a mapping table, and (b) the operation principle. 9 Fig. 2 5 (a) TCXO with a single varactor compensation, and (b) the operation principle. 10 Fig. 2 6 Proposed PPV-TCS operation concept. 11 Fig. 2 7 Block diagram of the proposed TCXO 12 Fig. 2 8 Model of the crystal employed in this work with additional capacitance loadings. 14 Fig. 2 9 Plot of XO frequency inaccuracy over temperature 15 Fig. 2 10 Schematic of the crystal oscillator and buffer stage. 16 Fig. 2 11 Current generator uses (a) constant-gm circuit; (b) bandgap circuit. 18 Fig. 2 12 Simulated PTC current generations using the constant-gm circuit and the BG circuit. 18 Fig. 2 13 (a) Schematic of the resistor-based PTC voltage generator; (b) type of resistors adopted to form the RPTC. 20 Fig. 2 14 PTC voltage generator simulation results. 21 Fig. 2 15 CNVC and CPVC varactors. 22 Fig. 2 16 Simulated capacitance of each varactor versus control voltage. 23 Fig. 2 17 Comparison of simulated PPV capacitance and calculated compensation capacitance. 23 Fig. 2 18 CPVC1 and CNVC mismatch Monte-Carlo simulation result (5000 points). 24 Fig. 2 19 Simulated CNVC, CPVC1, CPVC2 values vs. control voltages under 3 corners. 25 Fig. 2 20 Simulated CNVC trimming vs. control voltage VPTC. 26 Fig. 2 21 XO output amplitude versus varactor capacitance. 26 Fig. 2 22 Chip Photo. 27 Fig. 2 23 Measured XO swing (p-p) of the TCXO with and w/o ACL. 27 Fig. 2 24 Measured frequency error of the XO w/o PPV-TCS. 28 Fig. 2 25 Measured frequency error of the XO with PPV-TCS. 28 Fig. 2 26 Measured phase noise of the proposed TCXO. 30 Fig. 2 27 Simulated VPTC noise and the XO output noise due to VPTC. 30 Fig. 2 28 Buffer noise simulation result. 31 Fig. 2 29 Measured spectrum of the proposed TCXO. 32 Fig. 2 30 Measure current consumption of this work. 33 Fig. 3 1 IoT system reported in [15]. 34 Fig. 3 2 IoT system power profile reported in [16]. 35 Fig. 3 3 System operates in active mode and sleep mode with conventional LFXO. 36 Fig. 3 4 Tuning-fork kHz-range crystal temperature characteristic. 36 Fig. 3 5 System operates in active mode and sleep mode with dividing HFXO solution. 37 Fig. 3 6 (a) Relaxation oscillator reported in [19], and (b) oscillator with sophisticated temperature calibrations [20]. 37 Fig. 3 7 Simplified block diagram of the proposed system-clock-assisted architecture. 38 Fig. 3 8 Operation Principle of the proposed system-clock-assisted 32.768 kHz generator. 39 Fig. 3 9 Block diagram of the proposed system-clock-assisted 32.768 kHz clock generator. 40 Fig. 3 10 Architecture of the calibration module and fOSC temperature curve. 41 Fig. 3 11 Architecture of the calibration module and fMHz temperature curve. 41 Fig. 3 12 Architecture of the calibration module and N+α temperature curve. 42 Fig. 3 13 Architecture of the calibration module and fout temperature curve without TS function. 42 Fig. 3 14 Proposed 32.768 kHz output clock without TS function and with TS function. 43 Fig. 3 15 Architecture of the calibration module and fOSC temperature curve with TS function. 44 Fig. 3 16 Architecture of the relaxation oscillator 45 Fig. 3 17 Low-power fractional-N PLL architecture. 47 Fig. 3 18 Temperature Sensor Design. 48 Fig. 3 19 Power system design. 49 Fig. 3 20 Native NMOS simulation results. 50 Fig. 3 21 PLL freq. gain AHDL simulation result under fOSC variation -2~+2%. 52 Fig. 3 22 fout frequency AHDL transient simulation result under fOSC variation -5~+5%. 52 Fig. 3 23 Real circuit system simulation result. 53 Fig. 3 24 Chip Photo. 55 Fig. 3 25 Average current consumption vs. calibration period, and current consumption pie chart. 55 Fig. 3 26 Measured time-domain current profile of proposed calibration. 56 Fig. 3 27 Measured temperature inaccuracy of HFXO. 56 Fig. 3 28 Measured temperature inaccuracy of on-chip OSC. 57 Fig. 3 29 Measured temperature inaccuracy of final output without TS function. 57 Fig. 3 30 Measured temperature inaccuracy of final output with TS function. 57 Fig. 3 31 Allan deviation measurement. 58 Fig. 4 1 Conventional sub-sampling PLL. 60 Fig. 4 2 SSPLL prior art [23]. 61 Fig. 4 3 Conventional sub-harmonically injection-locked PLL operation. 62 Fig. 4 4 SIPLL prior art [25]. 62 Fig. 4 5 (a) Conceptual block diagram of the SS-SIPLL; (b) conceptual timing operation, and (c) PN improvement. 64 Fig. 4 6 Block diagram of the proposed SS-SIPLL. 65 Fig. 4 7 Sequence of operation modes. 66 Fig. 4 8 Operation timing diagram of the proposed SS-SIPLL. 67 Fig. 4 9 Linear noise model of the proposed SS-SIPLL. 68 Fig. 4 10 Noise TFs with respect to various sources of the SS-SIPLL. 68 Fig. 4 11 VCO, SSBUF, VCOBUF, and SSPD designs. 69 Fig. 4 12 DTC and PG designs. 70 Fig. 4 13 VIC gain simulation result. 71 Fig. 4 14 VCO phase noise simulation result. 72 Fig. 4 15 Reference buffer noise simulation under 40 MHz input frequency. 72 Fig. 4 16 DTC noise simulation under 40 MHz operation frequency. 73 Fig. 4 17 Different injection timing without calibration simulation result. 74 Fig. 4 18 Injection timing calibration procedure simulation result. 75 Fig. 4 19 Different injection timing with calibration simulation result. 75 Fig. 4 20 Chip micrograph. 77 Fig. 4 21 Power consumption pie chart of the SS-SIPLL. 77 Fig. 4 22 Measured output phase noise. 78 Fig. 4 23 Measured output spectrum. 78 Fig. 4 24 Plot of jitter vs. power consumption. 79 Fig. 4 25 Plot of FOM vs. REF frequency. 79 Fig. 5 1 Four output clock systems adopting (a) XO solution and (b) PLL solution. 82 Fig. 5 2 For output clock systems adopting FOD solution. 83 Fig. 5 3 Fractional output divide without DTC compensation under N=4 and α=0.25. 84 Fig. 5 4 Fractional output divide with ideal DTC compensation under N=4 and α=0.25. 85 Fig. 5 5 Fractional output divide with DTC compensation under N=4, α=0.25, and DTC full range=1.2TIN. 85 Fig. 5 6 Fractional output divide with DTC compensation and DTC gain calibration under N=4 and α=0.25. 85 Fig. 5 7 DTC gain calibration target formula. 86 Fig. 5 8 DTC gain calibration prior art [34]. 88 Fig. 5 9 Two replica-DTC structure. 89 Fig. 5 10 One replica-DTC structure. 90 Fig. 5 11 Main path DTC operation. 91 Fig. 5 12 Sense VP operation waveform. 92 Fig. 5 13 Sense VN block operation waveform. 93 Fig. 5 14 Calibration with (a) the conventional 1-MMD structure; and (b) the dual-divider structure. 95 Fig. 5 15 Proposed Replica-DTC-free background calibration FOD. 96 Fig. 5 16 Output frequency versus divider ratio M. 97 Fig. 5 17 Output frequency versus calibration updated time. 97 Fig. 5 18 Output frequency versus frequency resolution. 98 Fig. 5 19 Simplified block diagram from α to DCWK. 100 Fig. 5 20 Bit number of KDTC versus resolution and gate count. 100 Fig. 5 21 KDTC versus output error under DTC with 15%, 20%, and 25% gain variation. 101 Fig. 5 22 Zoom-in KDTC versus output error under DTC with 20% gain variation. 101 Fig. 5 23 DTC versus output error under DTC gain with 20% variation and KDTC=KDTC,OPT. 102 Fig. 5 24 1-stage DTC. 103 Fig. 5 25 Segmented DTC DCW[8:4] operation. 104 Fig. 5 26 Segmented DTC DCW[3:0] operation. 104 Fig. 5 27 Simulated total delay of the DTC versus input code. 106 Fig. 5 28 Simulated DNL and INL of the DTC used in this work. 106 Fig. 5 29 The schematic of (a) conventional PVC and (b) proposed PVC. 108 Fig. 5 30 PVC leakage simulation result. 109 Fig. 5 31 PVC mismatch simulation result. 109 Fig. 5 32 PVC transient noise simulation result. 110 Fig. 5 33 Multi-modulus divider structure. 110 Fig. 5 34 Comparator schematic. 111 Fig. 5 35 Comparator offset simulation result. 112 Fig. 5 36 Eye diagram of the proposed DTC gain calibration process under DTC w/i 15% gain error (N=6, α=0.25). 113 Fig. 5 37 Output frequency waveform under DTC w/i 15%, 20%, and 25% gain error (N=6, α=0.25). 113 Fig. 5 38 FOD chip photo. 114 Fig. 5 39 Power consumption pie parts at 625-kHz and 192-MHz output frequency. 115 Fig. 5 40 Measured output 145.52 MHz output frequency with N=8, M=2, and α=0.25. 115 Fig. 5 41 Measured output 59.516 MHz output frequency with N=10, M=4, and α=0.00802. 116 Fig. 5 42 Instantaneous frequency switching measurement. 117 Fig. 5 43 Frequency modulation capability measurement. 117 Fig. 5 44 Measured 192 MHz output spectrum with setting N=6, M=2, α=0.25. 118 Fig. 5 45 Under setting N=9, M=2, α=0.25-(1/2^14), measured 129.8 MHz output spectrum (a) without calibration and (b) with calibration 119 Fig. 5 46 Under setting N=9, M=8, α=16/2^14, measured 33.3 MHz output spectrum (a) without calibration and (b) with calibration. 120 Fig. 5 47 Fractional division (α) versus spur performance measurement under N=9, M=8. 121 Fig. 5 48 Time domain jitter measurement without calibration (KDTC=0). 122 Fig. 5 49 Time domain jitter measurement without calibration (KDTC=0.78). 122 Fig. 5 50 Time domain jitter measurement with the proposed calibration. 123 Fig. 5 51 Phase noise measurement under output frequency 149.854 MHz. 123 Fig. 5 52 Phase noise measurement under output frequency 192 MHz. 124 Fig. 5 53 Plot of FOM comparison. 125 Fig. 5 54 Plot of area versus FoM comparison. 125 List of Tables Table 2 1 Negative resistance simulation summary results. 16 Table 2 2 Noise contributions of VPTC generated noise and XO output buffer noise with the measured noise. 31 Table 2 3 Performance Summary and Comparison of TCXO clock. 33 Table 3 1 Simulation result of resistor’s temperature coefficient and sheet resistance in TSMC 0.18μm PDK 46 Table 3 2 Designed parameters of the proposed PLL 47 Table 3 3 Corner simulation of power system. 50 Table 3 4 Performance Summary and Comparison of 32.768-kHz clock. 59 Table 4 1 Performance summary and comparison of low noise PLLs 80 Table 5 1 Simulated full delay range under different corners and temperatures 105 Table 5 2 Performance Summary and Comparison 126 " | |
| dc.language.iso | en | |
| dc.title | 高效節能時脈系統設計 | zh_TW |
| dc.title | Design of a High-Performance Energy-Efficient Clock Generation System | en |
| dc.date.schoolyear | 110-1 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Min-Pei Lin),呂良鴻(Sue-Huei Chen),李泰成,黃柏鈞,陳巍仁 | |
| dc.subject.keyword | 溫補震盪器,千赫茲震盪器,高效鎖相迴路,開迴路小數除頻器, | zh_TW |
| dc.subject.keyword | TCXO,kHz clock generator,high-performance PLL,fractional output divider, | en |
| dc.relation.page | 135 | |
| dc.identifier.doi | 10.6342/NTU202200083 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2022-01-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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