半金屬電極於二維材料邏輯電晶體之電特性研究

Abstract

要實現二維材料在半導體元件領域中的應用，必須證明元件的性能和製程的可行性。然而，由於費米能級釘扎效應，金屬與半導體介面處的位能障從根本上導致了高接觸電阻和不良的電流傳輸能力，限制了二維材料半導體的發展。在本文中，我們提出並驗證了半金屬電極結合二維半導體材料的概念，其有效抑制了費米能級釘扎效應，從而獲得高效能、低功耗的邏輯電晶體。 首先，在二維材料的製備技術上，我們開發出低溫電漿輔助化學氣相沉積法，成功提升石墨烯品質；接著，通過基板修飾和分子摻雜改善了石墨烯的導電特性，利用傳輸線模型來萃取已摻雜之石墨烯與金屬之接觸電阻，我們獲得最好的結果顯示N型摻雜以鈦作為電極其接觸電阻為0.26 kΩ·μm；P型摻雜以金作為電極其接觸電阻則為0.06 kΩ·μm；最後，在定性分析中，與純金屬電極相比，石墨烯作為與二硫化鉬的半金屬電極表現出最佳結果。 因此，我們擴展了對更多種類半金屬的研究，包括錫、鉍、銻等半金屬。本研究透過氦離子束微影技術，將元件通道微縮至35奈米，所有的二維材料場效電晶體均表現出卓越的短通道性能，也透過拉曼光譜分析、Y函數法與變溫電性量測等實驗加以驗證其顯著的提升機制來自於半金屬與二維材料間的載子交互作用，尤其是鉍電極，其強摻雜效應使「鉍-二硫化鉬」介面處的蕭特基能障高度接近於零，最終達到導通狀態電流密度為860 μA/μm，接觸電阻為0.38 kΩ∙μm，創下二維材料半導體元件領域中的世界紀錄，且已相當接近International Roadmap for Devices and Systems (IRDS) 指標中的矽基邏輯電晶體規格。這些成就為進一步微縮元件尺度和延續摩爾定律提供了一條切實可行的途徑。

A wide variety of two-dimensional (2D) materials covers broad electronic properties, including metals, semimetals, semiconductors, and insulators. In order to realize the future 2D semiconductor electronics, it is imperative to prove the process feasibility and device performance. Many of those 2D materials have demonstrated promising potential for electronic and optoelectronic applications. In this thesis, we focused on forming a low resistance metal-2D contact for high performance low power logic application. We proposed to adopt several specific semimetals as metal contact to 2D semiconductor materials, where the Fermi-level pinning effect could be relieved, thereby lowering the contact resistance (RC) to below 0.5 kΩ∙μm in 2D devices. In the second chapter, we at first developed a low-temperature plasma-enhanced chemical vapor deposition (CVD) process to successfully improve the film quality of graphene. The electrical properties of the fresh graphene could be further enhanced through substrate modification and molecular doping. Then we used graphene as the semimetal contact to molybdenum disulfide (MoS2) and demonstrated a higher current performance 5 times than pure metal contacts through the qualitative electrical analysis. In the following chapters, we expanded the research to other kinds of semimetals, including Tin (Sn), Bismuth (Bi), Antimony (Sb). All of them demonstrated superior short channel monolayer MoS2 field-effect-transistor (FET) performance that the Bi contact reached near zero Schottky barrier height, a low RC value of 0.38 kΩ∙μm, and a record high ON-state current density of 860 μA/μm at VDS = 1 V. Above device performance could be further boost through material and process optimization, allowing to satisfy the specification of Si logic transistors in the metrics of International Roadmap for Devices and Systems (IRDS). The achievement in this work also provides a practical pathway to enable further shrinkage of device scale and extend Moore’s law.