基於輕量級自供電裝置之間歇性運算方法

Abstract

智能嵌入式裝置所提供的應用已經成為人們日常生活中一部分，由於應用上的大規模數量以及裝置上的尺寸上限制，如何為這些輕量且為數眾多的裝置供電已成為一項關鍵挑戰。近年來，新興的能量攫取器技術已為這些裝置的供電提供一項替代方案使得裝置能從環境中獲取能量。但由於此類能源供給本質上並不穩定，因此使自供電設備間歇運行也會帶來系統設計的挑戰，包括在間歇性運算下能實現的性能、不穩定電源造成的頻繁運行中斷、非揮發性記憶體與處理器間效能不一致所導致的性能下降。為了應對性能上的挑戰，我們首先建構一個工作排程的優化問題，並提出兩種根據收集能量的工作排程演算法，最大化在具備動態頻率調整的自供電裝置的系統性能。在其中，我們基於動態編程提出了一個偽多項式時間最佳算法，以及一個近似演算法來使得工作排程所需的運行時間和系統性能之間可以進行動態的權衡。為了使自供電裝置能夠適應頻繁的電源故障，我們提出了一種系統設計，可以在沒有建立檢查點的情況下實現間歇供電系統運算。該設計利用混合記憶體中讀寫數據的特性，實現並發任務執行中資料的一致性和可序列化，同時最大化計算性能，並使得裝置在恢復電源後能快速回復系統。為了解決由於頻繁寫入非揮發性記憶體導致的性能下降，我們提出了一種根據混合記憶體和異構計算單元之間性能差距來設計數據讀寫的訪問協議。具體地來說，該協議通過針對混合記憶體上的不同數據操作自動調整處理器之間的同步策略來減少工作間的阻塞時間，並且減少高性能處理在操作非揮發性記憶體數據時所導致的性能下降。

Applications based on smart lightweight devices have become a ubiquitous part of daily life. Energy harvesting has emerged as a promising alternative to replace frequently recharging devices by humans. However, because the amounts of energy harvested from the environment are unstable, self-powered devices inherently run intermittently, which brings several design challenges, including how to maximize forward progress with unstable power supply, how to achieve resiliency with frequent power failures, and how to leverage heterogeneity of intermittent systems which are typically heterogeneous memories and cores. To maximize forward progress, we firsts model intermittent executions as a task scheduling problem and propose two task scheduling algorithms to maximize system performance achieved by DVFS-enabled self-powered devices. In particular, we propose a pseudopolynomial-time optimal algorithm based on dynamic programming, as well as an approximation algorithm that allows for a trade-off between running time of scheduling tasks and optimal system performance. To achieve resiliency to power loss, we propose a failure-resilient design which enables intermittent computing without checkpointing and data logging. The design allows concurrent task executions to maximize computation progress while ensuring data consistency and serializability of task executions. Moreover, we enable instant system recovery after power resumption by leveraging the characteristics of data in hybrid memory. To address the performance degradation due to frequent updates to non-volatile memory, we extend the design to be diversity-aware and leverages the performance gaps between hybrid memory and heterogeneous computing units. Specifically, the protocol reduces the blocking time by adaptively applying different synchronization strategies for different data access operations on hybrid memory and allowing updates from a high-speed core can be delegated to another core.