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Title: | 應用於多電子束直寫系統之無損電路單元壓縮方案 Lossless Cell-based Compression Scheme for Multiple E-Beam Direct Write Systems |
Authors: | Tse-Kai Chen 陳則凱 |
Advisor: | 陳中平(Chung-Ping Chen) |
Keyword: | 蝕刻,電子束,資料壓縮演算法,實體設計,光柵化,電路圖檔, Lithography,Electron Beam,Data Compression Algorithm,Physical Design,Rasterization,gdsII, |
Publication Year : | 2018 |
Degree: | 碩士 |
Abstract: | 由於製程演進,超大型積體電路的最小尺寸已逼近傳統光學製程的極限。繞射的問題,在越小尺寸的製程中越嚴重,所以生產成本也節節攀升。在眾多次世代製程系統中,電子束曝光因具有高解析度、無光罩和高性價比的特性,是製程的明日之星。
不過,要向多電子束曝光系統快速傳輸大量電路資料為一難解的瓶頸反應。例如要生產一個300mm的晶圓,假設要達到70WPH的生產速度,所傳輸到多電子束系統的資料速率將達到驚人的144Tb/s。所以本篇論文提出電路單元壓縮方案。我們在不同電路階層下尋找高重複性電路,藉此把它們做成壓縮單元,以供此方案的解碼器多次重複呼叫,來達成平行解壓縮運算和快速傳輸巨量資料。此外,我們也找出最佳的電路佈局切片來維持電路單元的完整,而良好的切割會加快解壓縮的過程。本論文中,我們用此方法壓縮一個電力線通訊晶片,是實驗室設計的類比電路。這個晶片大小約為2.66mm X 2.58mm,並使用TSMC 90製程製造。最後我們得出整體壓縮比可達10000倍,而解壓縮時間在電路布局區域與LineDiff Entropy [1] 相仿。一般情況下,我們更可預期電路單元壓縮方案是比LineDiff Entropy [1]快的。 因此方案概念簡單且有效率,它可以用在運算資源有限的系統中。最後我們的結果顯示,此方案可達到超高壓縮比和快速解壓縮,所以很適合多電子束曝光系統。 With the advance of technology, the feature size of Integrated Circuits(IC) are shrinking to the limit of conventional optical lithography systems. Diffraction has been a severe obstacle for cost-effective production. Among next-generation lithography systems, electron beam lithography has high potential due to its high resolution, maskless and cost-effective features. However, the transmission of enormous layout data to e-beam lithography systems becomes a bottleneck of the systems. For instance, if we want to produce a 300-mm wafer under the requirement of 70 WPH, the data rate between a data center and multiple e-beam machines will reach 144Tb/s. Therefore, the thesis presents a new lossless layout compression and decompression algorithm called Cell-based Compression Scheme. The scheme is designed for transferring high volume data and parallel decompression. It finds out cells that have high repetitiveness at different circuit hierarchies. Then, the algorithm compresses these cells as compression units. Afterwards, the decoder of the scheme decodes massive layout data by frequently calling these compression units. Besides, we figure out the best stripe size for the intactness of cells, which will speed up the decoding process. In the thesis, we utilize Cell-based method to compress a powerline communication chip which is an analog circuit and is designed by our lab. The chip is 2.66mm X 2.58mm in size and is fabricated under TSMC 90. Last, we conclude that the compression ratio reaches 10000x and the decoding time as fast as LineDiff Entropy [1] in layout covered regions. In general case, we can expect Cell-based method is faster than LineDiff Entropy in decoding. Because the algorithm is simple and effective, the decoder of Cell-based Compression Scheme can be implemented with limited computing resources. The benchmark shows it has really high compression ratio and is capable of fast decoding. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77572 |
DOI: | 10.6342/NTU201802548 |
Fulltext Rights: | 未授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
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ntu-107-R03943130-1.pdf Restricted Access | 5.1 MB | Adobe PDF |
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