具權重容錯能力之深度神經網路加速器

Abstract

近年來機器學習領域蓬勃發展，深度神經網路應用於物聯網能處理大量的資料，為增進能源效率及減少網路頻寬需求，針對深度神經網路最佳化的硬體加速器成為物聯網不可或缺的一部份。然而，深度神經網路需要大量的記憶體以儲存權重，當降低操作電壓時，記憶體容易發生錯誤，在先進製程尤其明顯，此特性限制了能效進步的空間，需要妥善的處理。

本論文在系統層面藉由對權重參數做極端精確度縮放找出深度神經網路中可以運用的額外資源，並配合飽和量化避免放大錯誤效果，再使用位元敏感度分析及重複編碼有效率的應用多出來的位元空間以保護較重要的資訊。硬體層面以28奈米CMOS製程實現具備權重容錯能力的深度神經網路加速器，包含可配置的乘加器及多數投票器以適用於不同的精確度及不同位元的重複編碼。透過本論文提出的方法，在MNIST測資95\%預測正確率下，能容忍15\%權重位元錯誤，配合電壓縮放，操作在0.66V、323MHz，能效可達到261.5nJ/prediction。

In recent years, machine learning capabilities develop rapidly. Deep neural networks (DNN) can analyze a large amount of different-type data in the Internet of Things system. To improve energy efficiency and reduce Internet bandwidth, ASICs for DNN are necessary. However, DNNs require large-sized SRAMs to store weight parameters, which would be unstable at a reduced supply voltage, especially in the advanced technology node. SRAM errors limit the energy efficiency if the ASIC is not designed properly.

In this work, a system-level solution is proposed. First, to get additional space for redundancy, extreme precision scaling with saturated quantization is applied. Then, bit-level sensitivity analysis and repetition code are applied to protect more important information. A 28-nm CMOS weight-error-resilient DNN accelerator test chip with configurable multiply accumulators and configurable majority voters is designed for hardware performance and overhead evaluation. With the proposed method, the DNN accelerator can tolerate 15\% weight bit errors with 95\% prediction accuracy for MNIST dataset. With voltage scaling, the chip can achieve 261.5nJ per prediction operated at 0.66V, 323MHz.