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標題: | 針對5G收發機毫米波寬頻高線性度
雙刀雙擲開關之研製 A Broadband High Linearity TR switch for 5G Transceiver |
作者: | Shih-Shan Lo 羅仕善 |
指導教授: | 曹恆偉(Hen-Wai Tsao) |
關鍵字: | 單刀雙擲切換器,雙刀雙擲切換器,高線性度射頻開關電路,整合濾波器切換器,5G通訊系統,射頻前端,接收/發射開關, SPDT,DPDT,Filter-Integration Systems,T/R switches,high linearity,5G communications system,RF front-end, |
出版年 : | 2017 |
學位: | 碩士 |
摘要: | 本論文包括毫米波雙刀雙擲切換器的設計,以及其後續改進的研究。
本論文的第一部分說明射頻切換器的基本概念,進而介紹目前所使用的各大類射頻切換器工作的模式以及其優缺點。 第二部分則是介紹我們所設計的雙刀雙擲切換器,第一個版本的雙刀雙擲切換器為改版單刀雙擲切換器來達到雙刀雙擲,第二個版本的雙刀雙擲則採用整合濾波器的方式設計,使用此方法可進一步提升雙刀雙擲濾波器的線性度,除此之外可以針對不同要求來達到高隔離度以及頻段匹配。使用互補式金屬氧化半導體製程是現今整合系統於晶片(SOC)上的趨勢。本論文提出的第一個雙刀雙擲切換器使用1P6M 40奈米CMOS製程,在頻率0.1GHz到30GHz的頻率之間,其插入損耗的量測值約在4.5 dB,而隔離度優於20 dB,線性度P1dB約在12dBm ,另外一個雙刀雙擲切換器則使用1P10M 40奈米的CMOS製程製作,在頻段11 GHz 到30 GHz的頻率之間,其插入損耗的量測值約在4.2到5 dB之間,隔離度優於20 dB,而P1dB則優於20 dBm;就我們所知,此線性度是目前40奈米CMOS製程當中已知最高的。 第三個部分則是未來展望以及結論。 This thesis includes the design of millimeter-wave band DPDT(double-pole double throw) switches and the improvement of these circuits. The first part of this thesis illustrates the basic concepts of ratio frequency(RF) switches and then demonstrates the advantage of various kinds of RF switches. In the second part of this thesis we will illustrate the two versions of DPDT switches proposed by us. The first version of DPDT switches is based on the general series-shunt single-pole double-throw(SPDT) switches, we modify its structure and achieve the DPDT switching function. The second version DPDT was design by filter-integration method. The linearity of the DPDT could be enhanced by using that approach. Besides, the different requirements can be met to achieve high isolation and impedance matching. The CMOS process is a trend for system on chip(SOC). The first DPDT switch was designed in 1P6M 40 nm CMOS process, and it achieved an insertion loss of about 4.5 dB, isolation better than 20 dB in 10 MHz-30GHz band and had P1dB about 13 dBm. The second DPDT switch has an insertion loss about 4.2 - 5 dB, isolation better than 20 dB and P1dB better than 20 dBm in 11-30 GHz band. As far as we know, the second DPDT switch has the best P1dB reported in 40 nm CMOS process. The third part of the thesis is about conclusion and future work |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/7688 |
DOI: | 10.6342/NTU201703641 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 電子工程學研究所 |
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檔案 | 大小 | 格式 | |
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ntu-106-1.pdf | 2.15 MB | Adobe PDF | 檢視/開啟 |
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