請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/7584
標題: | 低靜態電流且具快速暫態響應之漣波耦合固定導通時間降壓轉換器設計與實現 Design and Implementation of A Ripple-Coupling Constant On-Time Controlled Buck Converter with Low-Quiescent Current and Fast Transient Response |
作者: | Jheng-An Juan Lu 阮呂政安 |
指導教授: | 陳景然(Ching-Jan Chen) |
關鍵字: | 低功率降壓型轉換器,高度數位化控制器,寬負載範圍,電荷幫浦,動態偏壓,電容電流固定導通時間控制之降壓轉換器, low-power buck converter,charge pump,constant on-time control,highly digital control,low quiescent current,wide load range,dynamic bias, |
出版年 : | 2020 |
學位: | 碩士 |
摘要: | 市面上越來越多的低功率降壓轉換器被應用於手持式裝置以及物聯網裝置,像是手機、電子智慧手環、心律血壓偵測器…等。由於這類產品需要能長時間使用並且這些裝置大部分時間都處於待機且低負載的狀態,所以其降壓轉換器需要能應付寬廣的負載範圍變化以及有良好的輕載效率。然而在輕載效率下,降低控制器的功率損耗將會是低功率之降壓轉換器的一大難題。本論文提出一高度數位化之降壓轉換器控制積體電路,其動態負載範圍為1.25x〖10〗^5,且在100μA負載電流下仍有85%以上的效率。控制積體電路主要針對導通時間產生器、補償器以及電容電流感測器電路做改良,導通時間產生器以數位的方式實現,使其可以隨負載下降功耗。補償器則利用電荷幫浦式誤差放大器及動態偏壓電路來降低偏壓電流的消耗。電容電流感測器利用全被動元件感測電流,取代傳統放大器組成的感測器。上述所提出之電路,使用台積電 0.18μm 製程實現,晶片面積為 1.2 平方毫米。第一個版本中實現了連續導通模式並且量測之峰值效率為88.5%。第二個版本中實現了連續導通模式以及不連續導通模式,模擬顯示控制器的總靜態電流為3.3μA,在10μA的負載下,效率為47%。當負載大於100μA,效率皆大於85%。 The low-power buck converters are widely used in consumer electronic products and Internet of Things products, such as electronic smart bracelets, heart rate detectors, etc. Since these devices need to be used for a long time and they operate in standby mode most of the time, the low-power buck converter needs to handle the wide load range and have good light load efficiency. However, under light load efficiency, reducing the power loss of the controller will be a major problem for low-power buck converters. This thesis proposed a highly digital controller buck converter with a dynamic load range of 1.25 x 〖10〗^5, and an efficiency of more than 85% at a load current of 100μA. The controller is mainly aimed at improving the on-time generator, compensator, and capacitive current sensor circuit. The on-time generator was implemented in a digital manner so that it can reduce power consumption with the load. The compensator was replaced by a charge pump-based error amplifier and a dynamic bias circuit to reduce the consumption of bias current. The capacitor-current sensor was implemented by fully passive components, instead of the amplifier-based current sensor. The proposed control was fabricated in an integrated circuit using 0.18 μm TSMC CMOS process with the chip area is 1.2mm^2. In the first version, the CCM part was implemented and the peak efficiency was measured to be 88.5%. In the second edition, CCM and DCM were implemented. The simulation showed that the total quiescent current of the controller consumes 3.3 μA, and the efficiency is 47% under 10 μA load current. When the load current is greater than 100μA, the efficiency is larger than 85%. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/7584 |
DOI: | 10.6342/NTU202000931 |
全文授權: | 同意授權(全球公開) |
電子全文公開日期: | 2023-06-05 |
顯示於系所單位: | 電機工程學系 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-109-1.pdf | 5.4 MB | Adobe PDF | 檢視/開啟 |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。