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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Chih-Chieh Ko | en |
dc.contributor.author | 葛致杰 | zh_TW |
dc.date.accessioned | 2021-05-19T17:42:52Z | - |
dc.date.available | 2024-02-12 | |
dc.date.available | 2021-05-19T17:42:52Z | - |
dc.date.copyright | 2019-02-12 | |
dc.date.issued | 2019 | |
dc.date.submitted | 2019-01-29 | |
dc.identifier.citation | [1] B. A. Miwa, D. Otten, and M. Schlecht, “High efficiency power factor correction using interleaving techniques,” in Proc. IEEE Appl. PowerElectro. Conf. and Expo. (APEC), 1992, pp. 557–568.
[2] C. Huang and P. Mok, “A 100 MHz 82.4% efficiency package-bondwire based four-phase fully-integrated buck converter with flying capacitor for area reduction,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 2977–2988, Dec. 2013. [3] C. K. Teh, A. Suzuki, M. Yamada, M. Hamada, and Y. Unekawa, “A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control,” in IEEE Int. Solid-State Circuits Conf. Dig.Tech. Papers, 2014, pp. 78–79. [4] A. Peterchev, J. Xiao, and S. Sanders, “Architecture and IC implementation of a digital VRM controller,” IEEE Trans. Power Electron., vol. 18, no. 1, pp. 356–364, Jan. 2003. [5]P. Li, L. Xue, P. Hazucha, T. Karnik, and R. Bashirullah, “A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters.,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3131–3145, Nov. 2009. [6] O. Garcia, P. Zumel, A. de Castro, and J. Cobos, “Automotive DC-DC bidirectional converter made with many interleaved buck stages,” in IEEE Transactions on Power Electronics, vol. 21, no. 3, pp. 578–586, May 2006. [7] Y. W. Huang, T. H. Kuo, S. Y. Huang and K. Y. Fang, “A Four-Phase Buck Converter With Capacitor-Current-Sensor Calibration for Load-Transient-Response Optimization That Reduces Undershoot/Overshoot and Shortens Settling Time to Near Their Theoretical Limits,” IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 552-568, Feb. 2018. [8] Y. P. Su, W. C. Chen, Y. P. Huang, C. Y. Chen, C. L. Ni and K. H. Chen, “Time-Shift Current Balance Technique in Four-Phase Voltage Regulator Module with 90% Efficiency for Cloud Computing,” IEEE Transactions on Power Electronics, vol. 30, no. 3, pp. 1521-1534, March 2015. [9] Robert Erickson and Dragan Maksimovic, “Fundamentals of Power Electronics,” 2nd Edition, Kluwer Academic Publishers, 2001. [10] Ke-Horng Chen, “Power Management Techniques for Integrated Circuit Design,” First Edition, John Wiley & Sons Singapore Pte Ltd, 2016. [11] R. Redl and J. Sun, 'Ripple-Based Control of Switching Regulators—An Overview,' in IEEE Transactions on Power Electronics, vol. 24, no. 12, pp. 2669-2680, Dec. 2009. [12] Cheung Fai Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” in IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 3-14, Jan. 2004. [13] K. Ryu, D. H. Jung and S. O. Jung, “A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 9, pp. 1860-1870, Sept. 2012. [14] K. H. Ryu, S. K. Park, and S.-O. Jung, “A Dual-Edge Triggered Phase Detector for Fast-Lock DLL,” in Proc. 12th WSEAS Int. Conf. Circuits, 2008, pp. 197–201. [15] S. J. Kim, R. K. Nandwana, Q. Khan, R. C. N. Pilawa-Podgurski and P. K. Hanumolu, “A 4-Phase 30–70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator,” in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2814-2824, Dec. 2015. [16] B. Lee, M. K. Song, A. Maity, and D. B. Ma, “A 25 MHz 4-phase SAW Hysteretic DC-DC Converter with 1-cycle APC Achieving 190 ns tsettle to 4 A Load Transient and Above 80% Efficiency in 96.7% of the Power Range,” IEEE ISSCC Dig. Tech. Papers, Feb. 2017, pp. 190–191. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/7398 | - |
dc.description.abstract | 本論文提出了一個快速鎖定延遲鎖定迴路應用於暫態調變固定導通時間控制之四相位降壓型轉換器,並且提出了一個新穎的電感電流均流校正技術,稱為脈衝寬度縮減技術,其可同時校正多相位轉換器中各相位脈衝寬度調變信號的責任週期與相位差。
為了達到更快速的負載暫態響應,我們在延遲鎖定迴路中,採用改良式的雙緣觸發之相位偵測器,亦即自動切換單/雙緣觸發之相位偵測器,藉以達成快速鎖定的機制。 本研究使用之降壓型轉換器,操作於一千萬赫茲之切換頻率,並使用三百三十奈米亨利之電感與二十二微米法拉之電容。輸入電壓為三點三伏特,輸出電壓為一點八伏特,而負載電流範圍為零點四安培到一點四安培。本作品在台積電零點一八微米互補式金屬氧化物半導體製程下,佔晶片面積六點一七毫米平方公尺。 | zh_TW |
dc.description.abstract | This thesis presents a fast-locking delay-locked loop (DLL) based four-phase DC-DC buck converter, which is manipulated by transient-modulated constant on-time control (TMCOT). Besides, a novel inductor current balancing method called pulse-width-shrunk technique (PWST) is proposed and it is capable of simultaneously calibrating the duty cycle and the phase error of pulse-width modulation (PWM) signals in the DLL-based multi-phase converter.
For the sake of much faster load transient response, the DLL adopts a modified dual edge triggered phase detector (DET-PD), namely automatic switching single/dual edge triggered phase detector (ASS/DET-PD), to accomplish the fast-locking mechanism. The buck converter is operated at 10 MHz switching frequency, and it employs a 330 nH inductor and a 22 μF output capacitor. The input voltage is 3.3V, and the output voltage is 1.8V. The load current ranges from 0.4A to 1.4A. The fully-integrated circuit is implemented in TSMC 0.18-μm CMOS process and the chip area is 6.17mm^2. | en |
dc.description.provenance | Made available in DSpace on 2021-05-19T17:42:52Z (GMT). No. of bitstreams: 1 ntu-108-R04943029-1.pdf: 6824696 bytes, checksum: 83c67338a5ff9848279ae74ab7e903f1 (MD5) Previous issue date: 2019 | en |
dc.description.tableofcontents | 中文審定書 i
英文審定書 iii 致謝 v 摘要 vii Abstract ix List of Figures xiii List of Tables xviii Chapter1 Introduction 1 1-1 Research Motivation 1 1-2 Thesis Overview 3 Chapter2 Fundamentals of DC-DC Buck Converter 4 2-1 Operation Concept of Buck Converter 4 2-2 Fixed-frequency Control 7 2-2-1 Voltage-mode Control (VMC) 9 2-2-2 Current-mode Control (CMC) 11 2-3 Ripple-based Control 14 2-3-1 Hysteretic Control 16 2-3-2 Constant On-time Control 18 Chapter3 Transient-modulated Constant On-time Controlled Single-phase Buck Converter 20 3-1 Architecture of Proposed Single-phase Buck Converter 20 3-2 Transient-modulated Constant On-time Control (TMCOT) 25 Chapter4 System Architecture and Proposed Techniques 28 4-1 Overall System Architecture 28 4-2 Fast-locking Delay-locked Loop (DLL) 31 4-3 Numerical Analysis of Fast-locking Theme 39 4-4 Effects of Duty Cycle and Phase Error Mismatch 44 4-5 Pulse-width-shrunk Technique (PWST) 49 Chapter5 Simulation and Measurement Results 52 5-1 Pre-simulation Results 52 5-2 Post-simulation Results 59 5-3 Measurement Results 66 5-3-1 Measurement Setup 68 5-3-2 Measurement Waveforms 71 Chapter6 Conclusion and Future Work 74 6-1 Conclusion 74 6-2 Future Work 74 Reference 75 | |
dc.language.iso | en | |
dc.title | 具電感電流均流校正技術之快速鎖定延遲鎖定迴路應用於暫態調變固定導通時間控制之四相位降壓型轉換器 | zh_TW |
dc.title | An Inductor Current Balancing Technique for Fast-locking Delay-locked Loop Based Four-phase Buck Converter with Transient-modulated Constant On-time Control for Fast Load Transient Response | en |
dc.type | Thesis | |
dc.date.schoolyear | 107-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳秋麟,羅有綱,林景源 | |
dc.subject.keyword | 四相位降壓型轉換器,快速鎖定延遲鎖定迴路,固定導通時間控制,均流,快速負載暫態響應, | zh_TW |
dc.subject.keyword | Four-phase buck converter,Fast-locking delay-locked loop (DLL),Constant on-time control,Current balancing,Fast load transient response, | en |
dc.relation.page | 76 | |
dc.identifier.doi | 10.6342/NTU201900285 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2019-01-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
dc.date.embargo-lift | 2024-02-12 | - |
顯示於系所單位: | 電子工程學研究所 |
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