以0.18微米互補式金氧半製程設計應用於S頻段雷達射頻系統單晶片之差動饋入低雜訊放大器與數位衰減器

Abstract

本論文以0.18微米互補式金氧半製程實現應用於S頻段差動饋入接收機系統之低雜訊放大器和數位衰減器，包含其電路設計與量測，以及接收器系統的整合。 首先是S頻段差動饋入之低雜訊放大器，操作頻率範圍為3.1至3.5 GHz，論文主要貢獻在於設計小尺寸但高增益的低雜訊放大器，因此設計兩級但增益仍達近18 dB，且在電路佈局中將兩個電感環繞在一起以節省面積。 接著是差動饋入數位衰減器，論文主要貢獻在於提出一種創新的架構，不同點為其設計的級間電路本身包含一個差動放大器以及緩衝放大器，此級間電路具有消除各級之間阻抗影響的功能，使數位衰減器各級間的衰減量互不影響，進而提升衰減器的精確度，並且此架構能降低衰減器的介入損耗。 最後則是S頻段(3.1到3.5 GHz)差動饋入接收機的系統整合，各元件間的級間電路亦是採用差動放大器加上緩衝放大器之架構去消除阻抗不匹配的影響，各元件在級間電路的隔離下皆能正常工作，接收機的輸出功率亦是本篇論文重要的指標，然而一些元件的介入損耗太大以及其1 dB增益壓縮時的輸入功率(IP1dB)不足，均使接收機的輸出功率過小，而未能滿足設計目標。

In this thesis, we demonstrate the design and measurement results of a low noise am-plifier (LNA) and digital attenuators applied to a S-band receiver with differential feed using 0.18-μm CMOS process. Furthermore, the integration of the receiver system is also demonstrated. First, for the S-band differentially-fed low noise amplifier, the targeted operating frequency range is from 3.1 to 3.5 GHz. The main contribution of this thesis lies in de-signing the LNA with high gain while keeping a small chip size. A two-stage design of the LNA with nearly 18-dB gain is demonstrated, and a special layout technique is used by surrounding two individual inductors together to save die area. As for the differentially-fed digital attenuators, the contribution of this thesis lies in the novel structure of the inter-stage circuit we proposed. The difference of the inter-stage circuit is that it is composed of a differential amplifier and buffer amplifiers. The in-ter-stage circuit can eliminate the impedance influence caused by adjacent circuits so that the attenuation level of each stages do not affect each other, and thus the attenuator’s ac-curacy is enhanced. Also, this structure could lower the attenuator’s insertion loss. Lastly, for the integration of the S-band (3.1 to 3.5 GHz) differentially-fed receiver system. A differential amplifier subjoining buffer amplifiers is also used as inter-stage cir-cuits to remove the impedance mismatch. All the units can work properly thanks to the high isolation of inter-stage circuits. While the output power of the receiver is also an im-portant indicator, the large insertion loss and poor IP1dB due to some other components render the output power of the receiver system too small to meet our design goal.