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標題: | 具有時間交錯以及降低底板切換損失技巧的全積體化之高效率電容式直流電壓轉換器 A fully-integrated high efficiency Switched-Capacitor DC-DC Converter with time-interleaved and bottom-plate switching loss reduction technique |
作者: | Chun-Lian Chen 陳俊連 |
指導教授: | 陳信樹(Hsin-Shu Chen) |
關鍵字: | 全積體化,電容式直流電壓轉換器,時間交錯,底板切換損失,電荷重新分配與利用,MOS電容器, Fully integrated,Switched Capacitor DC-DC converter,Time-interleaved,Bottom-plate loss,Charge redistribution and recycling,MOS- type capacitor, |
出版年 : | 2020 |
學位: | 碩士 |
摘要: | 近年來,低功率消耗的穿戴式裝置晶片以及生醫上的晶片應用蓬勃發展,人們需要低成本小體積的直流電壓轉換器的解決方案。全電容式的直流電壓轉換器因為其體積與功率密度比起電感式的直流電壓轉換器更具有優勢而再度受到重視。在物聯網的應用上,電源管理晶片講求小面積以及高效率,然而高密度電容也往往伴隨著大的寄生電容,使得同時具備兩者優點也成為全電容式電壓轉換器設計的難題。 全積體化電容式直流電壓轉換器最大的挑戰在於輸出漣波以及電容的大小限制,此晶片透過使用time-interleaved (TI)架構,可以等效地提升切換頻率以減小輸出漣波,進一步減低所需輸出電容。而電容則是相對佔有一定面積,透過結合三者(MIM、MOM、MOS)電容以提升功率密度減小單位電容體積。而上述做法解決了面積的問題,但是電容本身也造成嚴重的底板損失(bottom-plate loss),本論文進一步使用bottom-plate switching (BPS)以及well-biasing technique (WBS)技巧去解決此問題。 本論文將介紹全電容式直流電壓轉換器的操作原理並詳細分析電容式轉換器各項能量損失來源,以了解電容式轉換器常見的問題。接者詳細介紹提及的TI、BPS、WBS以及電容佈局,透過結合以上的技巧幫助我們設計一個應用於物聯網的全積體化且高效率電源轉換器。 此晶片透過台積電0.18μm 1P6M High Voltage Mixed Signal CMOS製程實現,依據實驗結果,本晶片在瞬間抽載時,暫態反應時間約為0.4~0.6μs,負載電流範圍從100微安培(μA)到10豪安培(mA),BPS以及WBS可以有效減少65%底板切換損失以提升整體轉換效率4~5%,達最高效率為84%。 Recently, people need the solution of DC-DC converter that can save a lot of cost and size because the application of low power wearable devices and biomedical device flourish. People pay attention to Switched Capacitor (SC) DC-DC converters because it is more competitive on size and power density than inductive power converter. For IoT (Internet of Things) application, power management chip focus on high-efficiency and small area. However, high-density capacitor usually induces high parasitic capacitor, which will degrade power efficiency. Therefore, how to design and get both advantages in SC DC-DC converter is difficult issue. In fully integrated SC DC-DC converter, most difficulty challenge are output ripple and capacitor in fully integrated SC DC-DC converter generally. The proposed chip uses TI structure to increase switching frequency so that its output ripple can be lower and reduces needed output capacitor area. In flying capacitor, the proposed capacitor layout includes MIM-, MOM- and MOS capacitor that increases capacitance density. However, the proposed capacitor also induces critical bottom-plate loss. In order to achieve both a high-efficiency and fully integrated power converter, the thesis proposes BPS and WBS technique to solve this loss. The thesis explains the operation principles of SC DC-DC converter and analyze loss items of SC DC-DC converter. That will help us realize issue in conventional SC converter. Next, I will introduce TI, BPS, WBS and proposed capacitor layout in detail. Through combing above-mentioned technique, a fully integrated and high efficiency power converter will be implemented for IoT applications. The proposed chip is fabricated in TSMC 0.18 μm 1P6M High Voltage Mixed Signal CMOS process. It can provide fixed output voltage of 1.8V at loading is 100μA ~ 10mA when input voltage is 4V to 4.2V. In measurement results, BPS and WBS will effectively reduce 65% bottom-plate loss that will improve 4~5% in overall power efficiency. Therefore, the proposed chip can achieve 84% peak efficiency. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71694 |
DOI: | 10.6342/NTU202004308 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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U0001-2610202021345400.pdf 目前未授權公開取用 | 3.7 MB | Adobe PDF |
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