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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
dc.contributor.author | Chun-Lian Chen | en |
dc.contributor.author | 陳俊連 | zh_TW |
dc.date.accessioned | 2021-06-17T06:06:50Z | - |
dc.date.available | 2023-01-01 | |
dc.date.copyright | 2020-11-03 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-10-28 | |
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Steyaert, “Monolithic capacitiveDC-DC converter with single boundary–multiphase control and voltage domain stacking in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1715–1727, Jul. 2011. [7] H.-P. Le, S. R. Sanders, and E. Alon, “Design techniques for fully integrated switched-capacitor DC-DC converters,” IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 2120–2131, Sep. 2011. [8] T. Van Breussegem and M. Steyaert, “A 82% efficiency 0.5% ripple 16-phase fully integrated capacitive voltage doubler,” in Proc. Symp. VLSI Circuits, Jun. 2009, pp. 198–199. [9] H. Meyvaert, T. Van Breussegem, and M. Steyaert, “A 1.65 W fully integrated 90nm bulk CMOS intrinsic charge recycling capacitive DC-DC converter: Design techniques for high power density,” in Proc. Of the IEEE Energy Conversion Congress and Exposition (ECCE), Phoenix, AZ, USA, Sep. 2011, pp. 3234–3241. [10] Chih-Hsien Chang, and Robert Bogdan Staszewski , Fellow, IEEE “A 180 mV 81.2%-Efficient Switched-Capacitor Voltage Doubler for IoT Using Self-Biasing Deep N-Well in 16-nm CMOS FinFET, ” IEEE J. Solid-State Circuits, vol. 1, no. 7, pp. 158–161, July. 2018. [11] T. M. Andersen et al., “A 4.6W/mm2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS,” in Proc. 28th Annu. IEEE Appl. Power Electron. Conf. Expo. (APEC), Mar. 2013, pp. 692–699. [12] Nicolas Butzen ; Michiel S. J. Steyaert “Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC–DC Converters, ” IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 2843–2853, Dec. 2016. [13] Y. K. Ramadass and A. P. Chandrakasan, “Voltage scalable switched capacitor DC-DC converter for ultra-low-power on-chip applications,” in Proc. 2007 IEEE Power Electronics Specialists Conf. (PESC), Jun. 2007, pp. 2353–2359. [14] Ramadass, Yogesh Kumar “Energy processing circuits for low-power applications,” Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009. [15] T. Van Breussegem et al., “A fully integrated gearbox capacitive DC/DC converter in 90nm CMOS: Optimization, control and measurements,” IEEE Control and Modeling for Power Electronics (COMPEL), June 2010. [16] Y. K. Ramadass, A. A. Fayed, and A. P. Chandrakasan, “A fully-integrated switched-capacitor step-down dc-dc converter with digital capacitance modulation in 45 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2557–2565, Dec. 2010. [17] S. S. Kudva, R. Harjani, “Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation Technique,” IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1910–1920, Aug. 2013. [18] L. G. Salem et al., “An 85%-efficiency fully integrated 15-ratio recursive switched-capacitor DC-DC converter with 0.1-to-2.2V output voltage range,” IEEE ISSCC Dig. Tech. Papers, pp. 88-89, Feb. 2014. [19] Junmin Jiang, Yan Lu, Cheng Huang, Wing-Hung Ki, Philip K. T. Mok1, “A 2-/3-Phase Fully Integrated Switched-Capacitor DC-DC Converter in Bulk CMOS for Energy-Efficient Digital Circuits with 14% Efficiency Improvement,” ISSCC Papers, pp. 366–367, Feb. 2015. [20] N. Butzen and M. Steyaert, “A 94.6%-efficiency fully integrated switched-capacitor DC-DC converter in baseline 40 nm CMOS using scalable parasitic charge redistribution,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), Jan. 2016, pp. 220–221. [21] Nicolas Butzen, Michiel Steyaert, “A 1.1W/mm2-Power-Density 82%-Efficiency Fully Integrated 3:1 Switched-Capacitor DC-DC Converter in Baseline 28nm CMOS Using Stage Outphasing and Multiphase Soft-Charging,” ISSCC Papers, pp. 178–179, Feb. 2017. [22] G. Patounakis, Y. Li, and K. L. Shepard, “A fully integrated on-chip DC-DC conversion and power management system,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 443–451, Mar. 2004. [23] L. Chang, R. Montoye, B. Ji, A. Weger, K. Stawiasz, and R. Dennard,“A fully integrated switched-capacitor 2:1 voltage converter with regulation capability and 90% efficiency at 2.3 A/mm ,” in IEEE Symp. VLSI Circuits Dig., Jun. 2010, pp. 55–56. [24] M. D. Seeman and S. R. Sanders, “Analysis and optimization of switched-capacitor DC-DC converters,” IEEE Trans. Power Electronics, vol. 23, no. 2, pp. 841–851, Mar. 2008. [25] D. El-Damak, S. Bandyopadhyay, and A. P. Chandrakasan, “A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 374–375. [26] D. Maksimovic and S. Dhar, “Switched-capacitor DC-DC converters for low-power on-chip applications,” in Proc. 30th Annu. IEEE Power Electron. Specialists Conf. (PESC), vol. 1. Aug. 1999, pp. 54–59. [27] N. Butzen and M. Steyaert, “A 10.1W/mm2-power-density 82%-efficiency fully integrated 3:1 switched-capacitor DC–DC converter in baseline 28nm CMOS using stage outphasing and multi-phase soft-charging,” in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, 2017, pp. 178–179. [28] Nicolas Butzen and Michiel Steyaert, “MIMO Switched-Capacitor Converter using only Parasitic Capacitance with Scalable Parasitic Charge Redistribution,” in Proc. IEEE ESSCIRC Conf., pp. 445–448, Nov. 2016. [29] Y. Lu, J. Jiang, and W.-H. Ki, “A multiphase switched-capacitor DC–DC converter ring with fast transient response and small ripple,” IEEE J. Solid-State Circuits, vol. 52, no. 2, pp. 579–591, Feb. 2017. [30] T. Van Breussegem and M. Steyaert, CMOS Integrated Capacitive DC-DC Converters, Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-4280-6, Springer Science+Business Media New York 2013 [31] H.-P. Le, M. D. Seeman, S. R. Sanders, V. Sathe, S. Naffziger, and E. Alon, “A 32 nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55 W/mm at 81% efficiency,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 210–211. [32] M. Seeman and S. R. Sanders, “Analysis and optimization of switched-capacitor DC-DC converters,” in Proc. 10th IEEE Workshop on Computers in Power Electronics (COMPEL), Jul. 2006, pp. 216–224. [33] K. D. T. Ngo and R. Webster, “Steady-state analysis and design of a switched-capacitor DC-DC,” in Proc. PESC, 1992, vol. 1, pp. 378–385. [34] B. R. Gregoire, “A compact switched capacitor regulated charge pump power supply,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1944–1953, Aug. 2006. [35] B. H. Calhoun and A. P. Chandrakasan, 'Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm CMOS,' IEEE International Solid-State Circuits Conference, pp. 300-301, Feb. 2005. [36] Y. K. Ramadass and A. P. Chandrakasan, “Minimum Energy Tracking Loop with Embedded DC-DC Converter Delivering Voltages down to 250mV in 65nm CMOS,” IEEE International Solid-State Circuits Conference, pp. 64-65, Feb. 2007. [37] W. Jung, S. Oh, S. Bang, Y. Lee, Z. Foo, G. Kim, Y. Zhang, D. Sylvester, and D. Blaauw, “An Ultra-Low Power Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor Voltage Doubler,” IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2800–2811, Dec 2014. [38] J. Delos, T. Lopez, E. Alarcn, and M. A. M. Hendrix, “On the modeling of switched capacitor converters with multiple outputs,” in 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014, March 2014, pp. 2796–2803. [39] H. Meyvaert, G. V. Pique, R. Karadi, H. J. Bergveld, and M. S. J. Steyaert,“A Light-Load-Efficient 11/1 Switched-Capacitor DC-DC Converter with 94.7% Efficiency While Delivering 100 mW at 3.3 V,” IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2849–2860, Dec 2015. [40] W. Kim, M. S. Gupta, G.-Y. Wei, and D. Brooks, “System level analysis of fast, per-core DVFS using on-chip switching regulators,” in Proc. IEEE 14th Int. Symp. High Perform. Comput. Archit. (HPCA), Feb. 2008, pp. 123–134. [41] T. Andersen et al., “A 10 W on-chip switched capacitor voltage regulator with feedforward regulation capability for granular microprocessor power delivery,” IEEE Trans. Power Electron., vol. 32, no. 1, 2017, doi: 10.1109/TPEL.2016.2530745. [42] L. G. Salem and P. P. Mercier, “A recursive switched-capacitor DC-DC converter achieving 2N -1 ratios with high efficiency over a wide output voltage range,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2773–2787, Dec. 2014. [43] H. Meyvaert, T. Van Breussegem, and M. Steyaert, “A 1.65 W Fully Integrated 90 nm Bulk CMOS Capacitive DC–DC Converter With Intrinsic Charge Recycling,” IEEE Trans. Power Electron., vol. 28, No. 9, pp. 4327–4334, Sep. 2013. [44] M. D. Seeman, “A design methodology for switched-capacitor DC-DC converters,” Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Univ. California, Berkeley, Berkeley, CA, USA, May 2009. [Online]. Available: http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS- 2009-78.html | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71694 | - |
dc.description.abstract | 近年來,低功率消耗的穿戴式裝置晶片以及生醫上的晶片應用蓬勃發展,人們需要低成本小體積的直流電壓轉換器的解決方案。全電容式的直流電壓轉換器因為其體積與功率密度比起電感式的直流電壓轉換器更具有優勢而再度受到重視。在物聯網的應用上,電源管理晶片講求小面積以及高效率,然而高密度電容也往往伴隨著大的寄生電容,使得同時具備兩者優點也成為全電容式電壓轉換器設計的難題。 全積體化電容式直流電壓轉換器最大的挑戰在於輸出漣波以及電容的大小限制,此晶片透過使用time-interleaved (TI)架構,可以等效地提升切換頻率以減小輸出漣波,進一步減低所需輸出電容。而電容則是相對佔有一定面積,透過結合三者(MIM、MOM、MOS)電容以提升功率密度減小單位電容體積。而上述做法解決了面積的問題,但是電容本身也造成嚴重的底板損失(bottom-plate loss),本論文進一步使用bottom-plate switching (BPS)以及well-biasing technique (WBS)技巧去解決此問題。 本論文將介紹全電容式直流電壓轉換器的操作原理並詳細分析電容式轉換器各項能量損失來源,以了解電容式轉換器常見的問題。接者詳細介紹提及的TI、BPS、WBS以及電容佈局,透過結合以上的技巧幫助我們設計一個應用於物聯網的全積體化且高效率電源轉換器。 此晶片透過台積電0.18μm 1P6M High Voltage Mixed Signal CMOS製程實現,依據實驗結果,本晶片在瞬間抽載時,暫態反應時間約為0.4~0.6μs,負載電流範圍從100微安培(μA)到10豪安培(mA),BPS以及WBS可以有效減少65%底板切換損失以提升整體轉換效率4~5%,達最高效率為84%。 | zh_TW |
dc.description.abstract | Recently, people need the solution of DC-DC converter that can save a lot of cost and size because the application of low power wearable devices and biomedical device flourish. People pay attention to Switched Capacitor (SC) DC-DC converters because it is more competitive on size and power density than inductive power converter. For IoT (Internet of Things) application, power management chip focus on high-efficiency and small area. However, high-density capacitor usually induces high parasitic capacitor, which will degrade power efficiency. Therefore, how to design and get both advantages in SC DC-DC converter is difficult issue. In fully integrated SC DC-DC converter, most difficulty challenge are output ripple and capacitor in fully integrated SC DC-DC converter generally. The proposed chip uses TI structure to increase switching frequency so that its output ripple can be lower and reduces needed output capacitor area. In flying capacitor, the proposed capacitor layout includes MIM-, MOM- and MOS capacitor that increases capacitance density. However, the proposed capacitor also induces critical bottom-plate loss. In order to achieve both a high-efficiency and fully integrated power converter, the thesis proposes BPS and WBS technique to solve this loss. The thesis explains the operation principles of SC DC-DC converter and analyze loss items of SC DC-DC converter. That will help us realize issue in conventional SC converter. Next, I will introduce TI, BPS, WBS and proposed capacitor layout in detail. Through combing above-mentioned technique, a fully integrated and high efficiency power converter will be implemented for IoT applications. The proposed chip is fabricated in TSMC 0.18 μm 1P6M High Voltage Mixed Signal CMOS process. It can provide fixed output voltage of 1.8V at loading is 100μA ~ 10mA when input voltage is 4V to 4.2V. In measurement results, BPS and WBS will effectively reduce 65% bottom-plate loss that will improve 4~5% in overall power efficiency. Therefore, the proposed chip can achieve 84% peak efficiency. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T06:06:50Z (GMT). No. of bitstreams: 1 U0001-2610202021345400.pdf: 3793026 bytes, checksum: fd3b5bfda500d0886423ad6e8e56cede (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | Chapter 1 Introduction 1 1.1 Motivation 3 1.2 Thesis Organization 6 Chapter 2 Fundamentals Analysis of Switched-Capacitor DC-DC Converter 7 2.1 Introduction 7 2.1.1 Architecture of Switched Capacitor DC-DC Converter 9 2.1.2 Operation of Switched-Capacitor (SC) DC-DC Converter 10 2.2 Modeling and Analysis of Switched Capacitor DC-DC Converter 11 2.2.1 Output Impedance Model 12 2.2.2 Total Output Impedance 15 2.2.3 Loss Analysis 17 2.2.4 Model Simplification for Switched Capacitor DC-DC Converter 21 2.3 Control Technique of Switched Capacitor DC-DC Converter 22 2.3.1 Pulse Frequency Modulation 22 2.3.2 Capacitance Modulation 25 2.3.3 Pulse-Width Modulation 26 Chapter 3 Fully-Integrated Time-interleaved Switched-Capacitor DC-DC Converter with Bottom-Plate Switching (BPS) and Well-Biasing (WBS) Technique 27 3.1 Time-interleaved (TI) Switched-Capacitor DC-DC Converter 28 3.2 Bottom-Plate Switching (BPS) 34 3.3 Well-Biasing Technique (WBS) 40 3.4 Proposed Fully-integrated High-Efficiency Time-Interleaved Switched Capacitor DC-DC Converter with Bottom-Plate Switching and Well-Biasing techniques 41 3.4.1 Operation principle 42 3.4.2 Design Goal 43 Chapter 4 Circuit Implementation 45 4.1 Architecture 45 4.1.1 Time-Interleaved Switched-Capacitor Power Stage Core with Bottom-Plate Switches (BPS) 46 4.1.2 Latch-type voltage sense amplifier [6] 47 4.1.3 Non-overlapping Clock Generator and Decoder 48 4.1.4 Capacitive (Cascading) Level-shifter 49 4.1.5 Proposed Capacitor Layout 49 4.1.6 Ring Oscillator (RO) [6] 51 4.2 Simulation results 52 4.2.1 Steady state waveforms 52 4.2.2 Load Transient Response 56 4.2.3 Power efficiency 57 Chapter 5 Experimental Results 59 5.1 Chip Micrograph 59 5.2 Experimental Environment Setup 60 5.3 Measurement Results 62 5.3.1 Steady-State Waveforms 62 5.3.2 Transient Waveforms 64 5.3.3 Power Efficiency 66 5.4 Performance Summary 71 Chapter 6 Conclusion and Future Work 75 6.1 Conclusions 75 6.2 Future Work 75 REFERENCE 77 | |
dc.language.iso | en | |
dc.title | 具有時間交錯以及降低底板切換損失技巧的全積體化之高效率電容式直流電壓轉換器 | zh_TW |
dc.title | A fully-integrated high efficiency Switched-Capacitor DC-DC Converter with time-interleaved and bottom-plate switching loss reduction technique | en |
dc.type | Thesis | |
dc.date.schoolyear | 109-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳景然(Ching-Jim Chen),劉宗德(Tsung-Te Liu) | |
dc.subject.keyword | 全積體化,電容式直流電壓轉換器,時間交錯,底板切換損失,電荷重新分配與利用,MOS電容器, | zh_TW |
dc.subject.keyword | Fully integrated,Switched Capacitor DC-DC converter,Time-interleaved,Bottom-plate loss,Charge redistribution and recycling,MOS- type capacitor, | en |
dc.relation.page | 82 | |
dc.identifier.doi | 10.6342/NTU202004308 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2020-10-28 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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