適用於通訊系統下通道等化與數位預失真之高效能數位訊號處理架構

Abstract

在通訊系統中，通道等化與數位預失真在傳輸端與接收端各占很重要的腳色。隨著半導體廠商技術不斷進步，晶片往往需要更高的頻寬與速度。在晶片到晶片的背板有線傳輸當中，序列與解序列器(serdes)的設計，其速度必須跟上高性能處理器與高儲存容量固態硬碟的速度要求。然而，在背板上的銅導線有線傳輸存在像是符號間干擾(inter-symbol interference)的不理想效應，會干擾傳輸的訊號並造成效能的下降。一般來說，序列與解序列器(serdes)的設計包含等化器來消除不理想效應。迴饋決策等化器(decision feedback equalizer)是平衡效能與成本後，用來解決符號間干擾的理想候選者。然而，即便迴饋決策等化器是很有效率的架構，在下一世代有線通訊56G序列與解序列器的規範中(IEEE 802.3BS)，要展開迴饋決策等化器的迴饋迴圈是一大挑戰。因此在這篇論文中，我們著重於在維持有效的符號間干擾消除的同時，設計一個使用在高速應用介面的平行展開的迴饋決策等化器架構。 此外，功率放大器在傳輸端會造成非線性的信號失真，因此數位預失真是一個廣泛運用在傳輸端用來消除失真的重要元件之一。而許多產品為了低功耗的設計，功率放大器往往會選擇更多區間操作在非線性的失真區域。傳統方法的數位預失真很難去消除嚴重的非線性失真，進而造成效能上的損失。而近年來機器學習在諸多領域革命性的發展，將其運用在數位預失真上得到很好的效果。然而，其卻需要可觀的訓練時間，因此在這篇論文中，在神經網路輔助之數位預失真加上轉換層架構，在維持效能的同時減少訓練所需時間。 在這篇論文中，我們先介紹傳統用來消除符號間干擾的方法並分析，接著，透過展開迴圈的技巧設計迴饋決策等化器迴圈的展開架構、利用演算法化簡的方式改良前饋濾波器展開架構，降低其複雜度。其次，利用轉換層的方式讓神經網路輔助之數位預失真減少訓練時間。最後，我們總結本研究與未來發展方向。

Channel equalization and digital predistortion (DPD) play important roles at the receiver and transmitter in communication systems. Since the advance of semiconductor technology, chips require higher bandwidth and transmission speed during serdes design of chip-to-chip wired communication in backplane for the sake of keeping abreast of high-performance calculation and high-density storage. However, the copper wire in the backplane exists distortions such as inter-symbol interference (ISI), which severely interferes the transmitted signals and causes performance degradation. Conventionally, the serdes design includes the equalizer to eliminate the impairments, and a decision feedback equalizer (DFE) is an ideal candidate to effectively suppress the ISI after trade-off performance, cost, and latency issues. Even if DFE is an efficient scheme, its architecture suffers from challenges of unfolding the feedback loop, when increasing the transmission rate in the next generation 56Gbps serdes design standards (IEEE 802.3BS) in wired communication systems. Therefore, in this thesis, we focus on how to design a parallel (N-way) architecture of DFE for high-speed application while maintaining effective performance of eliminating ISI distortion. Besides, the power amplifier also induces nonlinear distortion at the transmitter and DPD is essential in transmitter design to eliminate the distortion. For the purpose of low-power saving design, the smaller back-off range is applied, which causes severe nonlinear distortion when signals operate in compressed region of power amplifier. However, traditional methods of DPD are hard to combat with severe nonlinear distortions and result in considerable performance degradation. Thanks to the evolutionary development in the fields of machine learning, many arts of neural network (NN) based DPD have developed. While the NN-based model provides good performance in power amplifier DPD, this model requires considerable time for training to reach convergence. Therefore, in this thesis, a low training overhead NN-based DPD with transformer layer architecture (TLA) is introduced, which reduce the training time while maintaining good error performance. In this thesis, we first introduce conventional methods of ISI equalization and analyze the trade-off. Next, through loop-unrolling techniques and simplifying the algorithm of feed-forward filter (FFF), we can design a parallel and low-complexity architecture of DFE for high-speed demands. Based on adding TLA to conventional NN-based DPD, we further propose a low training overhead architecture. Finally, we conclude the research and possible future work.