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標題: | 利用原子層沉積技術成長氮化物蝕刻終止層與閘極介面層之研究 Atomic Layer Deposition of Nitride for Interlayer on High-k Gate Stack and Etch-stop Layers |
作者: | Yu-Syuan Cai 蔡宇軒 |
指導教授: | 陳敏璋 |
關鍵字: | 原子層沉積技術,蝕刻終止層,電漿處理,高介電係數閘極介電層,緩衝層, atomic layer deposition(ALD),etching-stop-layer,plasma treatment,high-k gate dielectric,buffer layer, |
出版年 : | 2018 |
學位: | 碩士 |
摘要: | 本論文主要分為兩部分,首先第一部分透過原子層沉積技術成長氮化物薄膜作為蝕刻終止層,加入不同ALD處理提高氮化物薄膜折射率,從GIXRD繞射分析發現,在ALD製程中加入電漿處理,能夠提高氮化物薄膜的結晶性,進而增強薄膜抗蝕刻能力,並提高氮化物薄膜崩潰電場。此外在ALD製程中加入TMA-treatment能夠有效抑制氮化物薄膜的漏電流、提高氮化物薄膜崩潰電場。接著XPS成分分析薄膜內的鍵結情形,藉此解釋不同ALD製程的氮化物薄膜在電性及蝕刻率上的差異,發現氮化物薄膜經過TMA-treatment後,薄膜中氧含量變高,因此有較高的蝕刻速率,薄膜抗蝕刻能力下降。第二部分利用ALD技術沉積高介電係數介電層MOS元件,在氧化層與矽基板間插入氮化層做為緩衝層,抑制退火處理時氧原子向矽基板擴散形成low-k介面層,降低元件整體等效電容厚度,透過插入氮化層使得漏電流和參考組相比,下降約一個數量級,接著觀察不同厚度的緩衝層對於元件電性的影響,發現隨著氮化層厚度越厚,氧化層/氮化層之介面缺陷漸漸遠離矽基板,能有效減少平帶電壓位移、介面缺陷密度、電容遲滯等現象,可以透過調整沉積介電層的製程參數或是善用緩衝層能夠阻擋雜質原子的特性,以達到元件最佳化的目標。 This thesis is divided into two parts. In the first part, the nitride etching-stop-layer was improved by different ALD treatments. From the GIXRD analysis, the crystallinity of the nitride layer can be improved by plasma treatment which significantly enhances the capability to resist the chemical and physical etching. The breakdown field of the nitride layer is also increased after the plasma treatment. In addition, the leakage current density can be suppressed by the TMA-treatment. In order to explain the differences in electrical properties and etching rates of the nitride layer with different ALD processes, the XPS analysis reveals that the chemical states are shifted by the TMA-treatment, resulting in a higher etching rate. In the second part, the ALD technique was used to deposit high-k gate dielectrics in MOS capacitors. A lower the CET and leakage current was achieved by inserting the nitride layer at high-k/silicon interface, which effectively block the oxygen diffusion toward the interface to form the interfacial layer during the post-metal annealing process. Next, the effect of the buffer layer with different thickness on electrical properties was studied. Although the shift of the flat-band voltage, interfacial state density and hysteresis of the MOS capacitors with nitride buffer layers are slightly higher than those without the nitride buffer layer, the interface trap would keep away from the silicon substrate with increasing the thickness of the nitride layer. Therefore, the electrical properties such as the shift of flat-band voltage、interfacial state density and hysteresis can be further improved by the buffer layer to effectively block the oxygen diffusion, along with the optimization of ALD conditions. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70479 |
DOI: | 10.6342/NTU201802662 |
全文授權: | 有償授權 |
顯示於系所單位: | 材料科學與工程學系 |
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