半正規的工程改變命令方法

Abstract

在晶片設計的過程中，如果後期發現了設計瑕疵或有規格改變，工程改變命令是一個普 遍使用的方法。我們提出一個兩階段的半正規工程命令改變方法來解決這個問題。我們先在 兩個電路中找出最多的功能性配對，接著最佳化這些配對並產生最小的修補邏輯電路來修好 有問題的電路。我們利用了 FRAIG 技術搭配基於模擬回饋的區域電路功能配對演算法來得 到較好的配對，而這些較好的配對會減少所要修好有問題的電路的修補邏輯電路大小。實驗 結果顯示我們提出的方法能在合理的時間內產生小的修補邏輯電路來修好有問題的電路。

Engineering change order (ECO) is a popular technique for rectifying design errors and specification changes in late design stages. We present a two-phase semi-formal patch generation to rectify multiple errors. We first 1) discover the functional matches in two circuits, then 2) optimize and generate a patch circuit from the matches. The ECO engine in this thesis discovers functional and structural matches in two circuits by the FRAIG technique and the simulation-guided cut-matching algorithm. Then, the combinational equivalence checking technique combined with a linear-time selection heuristic is processed to minimize the patch size from the matches. The experimental results show that this ECO engine can rectify circuits with small patch size within reasonable runtime.