請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70347完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚 | |
| dc.contributor.author | Chia-Lin Hsieh | en |
| dc.contributor.author | 謝佳霖 | zh_TW |
| dc.date.accessioned | 2021-06-17T04:26:16Z | - |
| dc.date.available | 2023-08-21 | |
| dc.date.copyright | 2018-08-21 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-08-14 | |
| dc.identifier.citation | [1] M. Abadir, J. Ferguson, and T. Kirkland, “Logic design verification via test generation,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 7, no. 1, pp. 138–148, Jan. 1988.
[2] P.-Y. Chung and I. Hajj, “Accord: Automatic catching and correction of logic design errors in combinational circuits,” in Proc. Int. ITC, Sep. 1992, pp. 742–751. [3] A. Veneris and I. Hajj, “Design error diagnosis and correction via test vector simulation,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 12, pp. 1803–1816, Dec. 1999. [4] C.-C. Lin, K.-C. Chen, and M. Marek-Sadowska, “Logic synthesis for engineering change,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 3, pp. 282–292, Mar. 1999. [5] Y .-S. Y ang, S. Sinha, A. V eneris, and R. Brayton, “Automating logic rectification by approximate SPFDs,” in Proc. ASP-DAC, Jan. 2007, pp. 402–407. [6] A. Ling, S. Brown, S. Safarpour, and J. Zhu, “Toward automated ECOs in FPGAs,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 30, no. 1, pp. 18–30, Jan. 2011. [7] B.-H. Wu, C.-J. Yang, C.-Y. Huang, and J.-H. Jiang, “A robust functional ECO engine by SAT proof minimization and interpola- tion techniques,” in Proc. IEEE/ACM Int. Conf. ICCAD, Nov. 2010, pp. 729–734. [8] K. H. Chang, I. Markov, and V. Bertacco, “Fixing design errors with counterexamples and resynthesis,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 1, pp. 184–188, Jan. 2008. [9] K.-F. Tang, C.-A. Wu, P.-K. Huang, and C.-Y. Huang, “Interpolation- based incremental ECO synthesis for multi-error logic rectification,” in Proc. 48th ACM/EDAC/IEEE DAC, Jun. 2011, pp. 146–151. [10] K.-F. Tang, P.-K. Huang, C.-N. Chou and C.-Y. Huang, 'Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction,' Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp. 1567-1572. [11] S.-Y. Huang, K.-C. Chen, and K.-T. Cheng, “Autofix: A hybrid tool for automatic logic rectification,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 9, pp. 1376–1384, Sep. 1999. [12] D. Hoffmann and T. Kropf, “Efficient design error correction of digital circuits,” in Proc. ICCD, Sep. 2000, pp. 465–472. [13] D. Brand, “Incremental synthesis,” in Proc. IEEE/ACM ICCAD, Nov. 1994, pp. 14–18. [14] S. Krishnaswamy, H. Ren, N. Modi, and R. Puri, “DeltaSyn: An efficient logic difference optimizer for ECO synthesis,” in Proc. IEEE/ACM ICCAD, Nov. 2009, pp. 789–796. [15] A. Kuehlmann and F. Krohm, “Equivalence checking using cuts and heaps,” in Proc. 34th ACM/IEEE DAC, Jun. 1997, pp. 263–268. [16] A. Mishchenko, S. Chatterjee, and R. Brayton, “Fraigs: A unifying representation for logic synthesis and verification,” EECS Dept., UC Berkeley, Tech. Rep, 2005. [17] Q. Zhu, N. Kitchen, A. Kuehlmann, and A. Sangiovanni-Vincentelli, “SAT sweeping with local observability don’t-cares,” in Proc. 43rd ACM/IEEE DAC, Jul. 2006, pp. 229–234. [18] S.-L. Huang, W.-H. Lin, P.-K. Huang and C.-Y. Huang, 'Match and replace: A functional ECO engine for multi-error circuit rectification,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 3, pp. 467-478, March 2013. [19] D. Brand, “Verification of large synthesized designs,” in Proc. IEEE/ACM ICCAD, Nov. 1993, pp. 534–537. [20] J. Cong and Y.-Y. Hwang, “Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology map- ping,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 9, pp. 1077-1090, Sep. 2001. [21] https://en.wikipedia.org/wiki/Cosine_similarity [22] http://people.eecs.berkeley.edu/~alanmi/abc/ [23] N. So ̈rensson and N. Ee ́, “Minisat v1. 13: A SAT solver with conflict- clause minimization,” in Proc. SAT, 2005, pp. 53–54. [24] https://github.com/msoeken/iwls2017-contest [25] L.Amaru ́,P.-E.Gaillardon,andG.DeMicheli,“The epfl combinational benchmark suite,” in Proc. 24th International Workshop on Logic & Synthesis (IWLS), no. EPFL-CONF-207551, 2015. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70347 | - |
| dc.description.abstract | 在晶片設計的過程中，如果後期發現了設計瑕疵或有規格改變，工程改變命令是一個普 遍使用的方法。我們提出一個兩階段的半正規工程命令改變方法來解決這個問題。我們先在 兩個電路中找出最多的功能性配對，接著最佳化這些配對並產生最小的修補邏輯電路來修好 有問題的電路。我們利用了 FRAIG 技術搭配基於模擬回饋的區域電路功能配對演算法來得 到較好的配對，而這些較好的配對會減少所要修好有問題的電路的修補邏輯電路大小。實驗 結果顯示我們提出的方法能在合理的時間內產生小的修補邏輯電路來修好有問題的電路。 | zh_TW |
| dc.description.abstract | Engineering change order (ECO) is a popular technique for rectifying design errors and specification changes in late design stages. We present a two-phase semi-formal patch generation to rectify multiple errors. We first 1) discover the functional matches in two circuits, then 2) optimize and generate a patch circuit from the matches. The ECO engine in this thesis discovers functional and structural matches in two circuits by the FRAIG technique and the simulation-guided cut-matching algorithm. Then, the combinational equivalence checking technique combined with a linear-time selection heuristic is processed to minimize the patch size from the matches. The experimental results show that this ECO engine can rectify circuits with small patch size within reasonable runtime. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T04:26:16Z (GMT). No. of bitstreams: 1 ntu-107-R04943179-1.pdf: 1484139 bytes, checksum: 8aca39a08667795c527b3959b597e16c (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 摘要...i
Abstract...ii Chapter 1 Introduction...1 Chapter 2 Preliminaries...2 2.1 ECO Problem...2 2.2 Match-and-Replace Method...3 2.3 Miter & FRAIG...5 2.4 Boolean Matching...5 2.5 Circuit Functional Similarity...6 Chapter 3 Semi-Formal ECO Method...8 3.1 Overview of Our ECO Engine...8 3.2 Matching Phase — Patch Region Identification...10 3.2.1 Input-side Merging Frontier Identification...11 3.2.2 Output-side Frontier Identification...13 3.3 Replacing Phase — Patch Region Optimization...19 Chapter 4 Experimental Results...23 Chapter 5 Conclusions and Future Work...29 Reference...30 | |
| dc.language.iso | en | |
| dc.subject | 功能性配對 | zh_TW |
| dc.subject | 修補邏輯電路 | zh_TW |
| dc.subject | 工程改變命令 | zh_TW |
| dc.subject | Engineering change order | en |
| dc.subject | patch circuit | en |
| dc.subject | functional matches | en |
| dc.title | 半正規的工程改變命令方法 | zh_TW |
| dc.title | Semi-Formal ECO Method | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 江蕙如,李建模,鐘偉滋 | |
| dc.subject.keyword | 工程改變命令,功能性配對,修補邏輯電路, | zh_TW |
| dc.subject.keyword | Engineering change order,functional matches,patch circuit, | en |
| dc.relation.page | 32 | |
| dc.identifier.doi | 10.6342/NTU201803276 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-08-14 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-107-1.pdf 未授權公開取用 | 1.45 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。