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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70080| 標題: | 連續漸進式類比至數位轉換器與混合架構電源供應系統 A Subranging SAR ADC with Hybrid Power Supply System |
| 作者: | Li-Yu Huang 黃立宇 |
| 指導教授: | 陳信樹(Hsin-Shu Chen) |
| 關鍵字: | 混和架構電源系統,類比至數位轉換器,連續漸進式,高電能效益,無外掛電容, hybrid power system,analog-to-digital converter (ADC),successive-approximation register (SAR),energy-efficient,without external-decoupling capacitor, |
| 出版年 : | 2018 |
| 學位: | 碩士 |
| 摘要: | 近年來,隨著製程的進步,連續漸進式類比至數位轉換器速度較慢讓人詬病的問題獲得改善,靠著其低功耗的特色,已逐漸成為主流的類比至數位轉換器。在低功耗的連續漸進式類比至數位轉換器中,其品質因數以可達到毫微微的等級。相比之下,其電源供應端的電路功耗大幅超過了類比至數位轉換器本身。為了改善這個問題,本篇論文提出了一個與類比至數位轉換器同步的混和架構電源供應系統,可使電源供應端的效率大幅提升。
本作品的量測結果可使類比至數位轉換器同步操作在每秒四十萬轉換及輸入頻率為二十萬赫茲。包含電源供應系統與類比至數位轉換器,其主動面積只有0.0098mm2。在電源供應端不需外掛電容的情況下,整體功耗為334nW,換算FOMW為每步階轉換消耗1.63 fJ/conversion-step。其適合用在觸控與面板整合的電路設計之中。 In recent years, with the progress of the process, the low speed problem of subrange successive-approximation register (SAR) ADC has been improved. By virtue of it’s low power consumption characteristics, it has gradually become the mainstream analog-to-digital converter. In low-power SAR ADC design, the quality factor have achieved the femto level. In contrast, the power consumption of power supply circuit had significantly beyond the analog-to-digital converter. In order to ameliorate this problem, this essay propose a hybrid power supply system that is synchronized with the analog-to-digital converter. It can increase the efficiency of the power supply circuit dramatically. This proposed work can achieve the conversion rate of 400KS/s with 200 KHz input frequency. Including dynamic LDO and SAR ADC, The active area is only 0.0098 mm2. Without external-decoupling capacitor, it consumes 0.334nW and FoMW of 1.63fJ/conversion-step. It is suitable for touch with display driver integration (TDDI) module. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70080 |
| DOI: | 10.6342/NTU201800340 |
| 全文授權: | 有償授權 |
| 顯示於系所單位: | 電子工程學研究所 |
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| ntu-107-1.pdf 未授權公開取用 | 2.19 MB | Adobe PDF |
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