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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Li-Yu Huang | en |
| dc.contributor.author | 黃立宇 | zh_TW |
| dc.date.accessioned | 2021-06-17T03:42:25Z | - |
| dc.date.available | 2021-02-23 | |
| dc.date.copyright | 2018-02-23 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-02-05 | |
| dc.identifier.citation | [1] J. Shen, et al., “A 16-bit 16MS/s SAR ADC with On-Chip Calibration in 55nm CMOS,” IEEE Symp. VLSI Circuits, pp.C282-C283, Jun. 2017.
[2] Y.-Z Lin, et al., “A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with Fast Reference Charge Neutralization and Background Timing-Skew Calibration in 16-nm CMOS,” IEEE Symp. VLSI Circuits, pp.C204-C205, Jun. 2016. [3] M. Liu, et al., “A 0.8V 10b 80ks/S SAR ADC With Duty-Cycled Reference Generation,” IEEE ISSCC Dig. Tech. Papers, pp. 278-279, Feb. 2015. [4] H.-Y. Tai, et al., “A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 196-197, Feb. 2014. [5] C. H. Chan, et al., “60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration,” IEEE J. Solid-State Circuits, vol. 52, pp. 2576-2588, Oct. 2017. [6] Yasuyuki Okuma, et al., “0.5-V Input Digital LDO With 98.7% Current Efficiency and 2.7-µA Quiescent Current in 65nm CMOS,” IEEE CICC, pp. 1-4, Sept. 2010. [7] Maoqiang Liu, et al., “A 10b 20MS/s SAR ADC with a Low-Power and Area-Efficient DAC-Compensated Reference,” IEEE European Solid State Circuits Conference, pp. 231-234, Sept. 2017. [8] Prakash Harikumar, et al., “Design of a Reference Voltage Buffer For A 10-Bit 50 MS/S SAR ADC in 65 nm CMOS,” IEEE International Symposium on Circuits and Systems, pp. 249-252, July. 2015. [9] Yu-Huei Lee, et al., “A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement,” IEEE J. Solid-State Circuits, vol. 48, pp. 1018-1030, Jan. 2013. [10] Loai G. Salem, et al., “A 100nA-to-2mA Successive-Approximation Digital LDO with PD Compensation and Sub-LSB Duty Control Achieving a 15.1ns Response Time at 0.5V,” IEEE ISSCC Dig. Tech. Papers, pp. 340-341, Feb. 2017. [11] Weiwei Xu, et al., “A 1A LDO Regulator Driven by a 0.0013mm2 Class-D Controller,” IEEE ISSCC Dig. Tech. Papers, pp. 104-105, Feb. 2017. [12] Michael Cheah, et al., “A 100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO With Active Ripple Suppression,” IEEE Transactions on Very Large Scale Integration (VLSI), vol. 25, pp. 696-704, Aug. 2016. [13] M. V. Elzakker, et al., “A 10-Bit Charge Redistribution ADC Consuming 1.9uw at 1 MS/s,” IEEE J. Solid-State Circuits, vol. 45, pp. 1007-1015, May 2010. [14] Marcus Yip, et al., “A Resolution-Reconfigurable 5-to-10-Bit 0.4-to-1 V Power Scalable SAR ADC for Sensor Applications,” IEEE J. Solid-State Circuits, vol. 48, pp. 1453-1464, Apr. 2013. [15] F. Kuthner, et al.,“A 1.2V 10b 20MSample/s Non-Binary Successive Approximation ADC in 0.13µm CMOS” IEEE ISSCC Dig. Tech. Papers, pp. 176-177, Feb. 2002. [16] C.-C. Liu, et al., “A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation,” IEEE ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2010. [17] Ryota Sekimoto, et al., “A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, pp. 2628-2636, Aug. 2013. [18] Yan Zhu, et al., “Split-SAR ADCs: Improved Linearity With Power and Speed Optimization,” IEEE Transactions on Very Large Scale Integration (VLSI), vol. 22, pp. 372-383, Feb. 2014. [19] Y. J. Lee, et al., “A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual Loop in Mobile Application Processor,” IEEE ISSCC Dig. Tech. Papers, pp. 150-151, Feb. 2016. [20] C. C. Liu, et al., “A 10-Bit 320-MS/S Low-Cost SAR ADC for IEEE 802.11ac Applications In 20-nm CMOS,” IEEE J. Solid-State Circuits, vol. 50, pp. 2645-2654, Nov. 2015. [21] Y.-Z. Lin, et al., “A 1-uw 10-Bit 200-Ks SAR ADC With A Bypass Window For Biomedical Applications,” IEEE J. Solid-State Circuits, vol. 47, pp. 2783-2795, Nov. 2012. [22] B. P. Ginsburg, et al., “An Energy-Efficient Charge Recycling Approach For A SAR Converter With Capacitive DAC,” IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 184-187, Jun. 2005. [23] S. J. Chang, et al., “A 10-Bit 50-MS/S SAR ADC With A Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, pp. 731-740, Apr. 2010. [24] Yan Zhu, et al., “A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1111-1121, Jun. 2010 [25] T. Sepke, et al.,“Noise Analysis For Comparator-Based Circuits,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 3, pp. 541–553, Mar. 2009. [26] Liang-Jen Chen, et al., “A 12-bit 3.4 MS/s Two-Step Cyclic Time-DoMain ADC in 0.18-μm CMOS,” IEEE Transactions on Very Large Scale Integration (VLSI), vol. 24, pp. 1470-1483, Apr. 2016. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70080 | - |
| dc.description.abstract | 近年來，隨著製程的進步，連續漸進式類比至數位轉換器速度較慢讓人詬病的問題獲得改善，靠著其低功耗的特色，已逐漸成為主流的類比至數位轉換器。在低功耗的連續漸進式類比至數位轉換器中，其品質因數以可達到毫微微的等級。相比之下，其電源供應端的電路功耗大幅超過了類比至數位轉換器本身。為了改善這個問題，本篇論文提出了一個與類比至數位轉換器同步的混和架構電源供應系統，可使電源供應端的效率大幅提升。
本作品的量測結果可使類比至數位轉換器同步操作在每秒四十萬轉換及輸入頻率為二十萬赫茲。包含電源供應系統與類比至數位轉換器，其主動面積只有0.0098mm2。在電源供應端不需外掛電容的情況下，整體功耗為334nW，換算FOMW為每步階轉換消耗1.63 fJ/conversion-step。其適合用在觸控與面板整合的電路設計之中。 | zh_TW |
| dc.description.abstract | In recent years, with the progress of the process, the low speed problem of subrange successive-approximation register (SAR) ADC has been improved. By virtue of it’s low power consumption characteristics, it has gradually become the mainstream analog-to-digital converter. In low-power SAR ADC design, the quality factor have achieved the femto level. In contrast, the power consumption of power supply circuit had significantly beyond the analog-to-digital converter. In order to ameliorate this problem, this essay propose a hybrid power supply system that is synchronized with the analog-to-digital converter. It can increase the efficiency of the power supply circuit dramatically.
This proposed work can achieve the conversion rate of 400KS/s with 200 KHz input frequency. Including dynamic LDO and SAR ADC, The active area is only 0.0098 mm2. Without external-decoupling capacitor, it consumes 0.334nW and FoMW of 1.63fJ/conversion-step. It is suitable for touch with display driver integration (TDDI) module. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T03:42:25Z (GMT). No. of bitstreams: 1 ntu-107-R04943025-1.pdf: 2238183 bytes, checksum: b0297a4cff670ad38d4f0579a597b56f (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 致謝 I
摘要 II Abstract III List of Figures VI List of Tables VIII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converter 3 2.1 Introduction 3 2.2 Performance Metrics 3 2.2.1 Gain and Offset Error 4 2.2.2 Differential and Integral Nonlinearity (DNL and INL) 5 2.2.3 Signal-to-Noise Ratio (SNR) 6 2.2.4 Total Harmonic Distortion (THD) 8 2.2.5 Spurious Free Dynamic Range (SFDR) 8 2.2.6 Signal to Noise and Distortion Ratio (SNDR) 9 2.2.7 Effective Number of Bits (ENOB) 9 2.2.8 Figure of Merit (FoM) 10 2.3 ADC Architectures 11 2.3.1 Successive-Approximation-Register Architecture 11 2.3.2 Two-Step and Subranging Architecture 14 Chapter 3 Power Supply Circuit 16 3.1 Introduction 16 3.2 Low Dropout (LDO) Regulator 16 3.2.1 Dropout Voltage 18 3.2.2 Line Regulation 20 3.2.3 Load Regulation 21 3.2.4 Quiescent Current 22 3.2.5 Transient Response 24 3.2.6 Efficiency 29 3.3 Switched Capacitor (SC) DC-DC Converter 30 3.3.1 Charge Pump Method 31 Chapter 4 SAR ADC with Hybrid Power Supply System 35 4.1 Introduction 35 4.2 Proposed Architecture 36 4.3 Capacitor Switching Algorithm and Technique of ADC 41 4.3.1 Detect-and-Skip Algorithm 41 4.3.2 Aligned Switching Technique 46 4.3.3 Split-Monotonic Switching Method 48 4.4 Detective and Dynamic Control of System 51 4.4.1 On Chip Capacitor CDC 52 4.4.2 Detective Method and Dynamic Control 54 4.5 Charge Compensator 57 4.5.1 Analysis of Capacitor CCharge 58 4.6 Supply Reset (RST) Circuit 60 4.6.1 Self-Stop Loop Control 61 4.7 Reference Voltage Error Tolerance 64 4.7.1 Max Tolerance Range of Reference Voltage Error 64 4.8 Summary 65 Chapter 5 Experiment Results 67 5.1 Measurement Setup 67 5.2 Measurement Results 69 Chapter 6 Conclusion and Future Work 76 6.1 Conclusion 76 6.2 Future Work 77 Bibliography 78 | |
| dc.language.iso | en | |
| dc.subject | 連續漸進式 | zh_TW |
| dc.subject | 無外掛電容 | zh_TW |
| dc.subject | 混和架構電源系統 | zh_TW |
| dc.subject | 類比至數位轉換器 | zh_TW |
| dc.subject | 高電能效益 | zh_TW |
| dc.subject | hybrid power system | en |
| dc.subject | analog-to-digital converter (ADC) | en |
| dc.subject | successive-approximation register (SAR) | en |
| dc.subject | energy-efficient | en |
| dc.subject | without external-decoupling capacitor | en |
| dc.title | 連續漸進式類比至數位轉換器與混合架構電源供應系統 | zh_TW |
| dc.title | A Subranging SAR ADC with Hybrid Power Supply System | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳景然(Ching-Jan Chen),陳昭宏(Jau-Horng Chen) | |
| dc.subject.keyword | 混和架構電源系統,類比至數位轉換器,連續漸進式,高電能效益,無外掛電容, | zh_TW |
| dc.subject.keyword | hybrid power system,analog-to-digital converter (ADC),successive-approximation register (SAR),energy-efficient,without external-decoupling capacitor, | en |
| dc.relation.page | 81 | |
| dc.identifier.doi | 10.6342/NTU201800340 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-02-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-107-1.pdf 未授權公開取用 | 2.19 MB | Adobe PDF |
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