二點五維積體電路封裝設計之繞線系統

Abstract

二點五維積體電路 (2.5-dimensional integrated circuit) 是目前最常用的整合封裝技術之一，此封裝技術引進一個中介層 (interposer) 作為晶片與封裝之間的介面橋樑，並整合多個晶片於中介層上，而晶片之間的訊號傳輸則透過多層重分佈層 (redistribution layer) 來進行。傳統的電路設計中，訊號線只會有單一種類的線寬與間距，此種設計為網格式電路設計 (grid-based design)。然而隨著技術上的演進，為了將現今的電路設計發揮更好的效能，會採用多種線寬與間距的訊號線，而此種設計則為無網格式電路設計 (gridless design)。在此篇論文中，我們提出了第一個可以整合處理網格式和非網格式電路設計的重分佈層繞線問題的繞線架構，而此架構的演算法是建立在係數基底矩陣分裂疊代法 (modulus-based matrix splitting iteration method) 與二分圖連線匹配法 (bipartite matching) 之上，由係數基底矩陣分裂疊代法考慮多重的電路設計限制並計算出每條訊號線的初步位置，再由二分圖連線匹配法進一步優化位置。我們亦證明和驗證所提出的演算法在網格式電路設計上可以得到最佳解。實驗結果顯示我們的繞線器可以在網格式電路設計上達到百分之百的繞線率並得到最佳解，並比相關發表論文所延伸的演算法快數十倍，而我們的繞線器可以在非網格式電路設計上達到百分之百繞線率，相較之下，相關發表論文所延伸的演算法在非網格式電路設計上無法達到百分之百的繞線率，並且會使用更長的訊號線和數百倍的時間。我們的繞線架構極具有擴展性，可以透過簡易延伸應用到其他的繞線問題上。

A 2.5-dimensional integrated circuit, which introduces an interposer as an interface between chips and a package, is one of the most popular integration technologies. Multiple chips can be mounted on an interposer, and inter-chip nets are routed on redistribution layers (RDLs). In traditional designs, the wire widths and spacings are uniform (i.e., grid-based). To improve circuit performance in modern designs, however, variable widths and spacings are also often adopted (i.e., gridless). In this thesis, we propose the first unified routing framework that can handle both grid-based and gridless routing on RDLs based on the modulus-based matrix splitting iteration method (MMSIM) and bipartite matching. The MMSIM-based method assigns each wire a rough position while considering multiple design rules, and bipartite matching is applied to further refine those positions. We also prove the optimality of our RDL routing framework for grid-based designs and validate it empirically. Experimental results show that our framework can solve all the gridless and grid-based designs provided by industry effectively and efficiently. Compared with the previous method based on grid-based benchmarks, our routing framework achieves a 68X speedup while maintaining 100% routability and the optimal wirelength. For gridless benchmarks, our framework achieves a 274X speedup with 100% routability, while the previous method cannot. In particular, our framework is general and readily extends to other routing problems.