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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/69804| 標題: | 適用於稀疏碼多工存取與低密度奇偶檢查碼系統之迭代式偵測與解碼接收機設計與實作 Design and Implementation of an Iterative Detection and Decoding Receiver for LDPC-coded Sparse Code Multiple Access Systems |
| 作者: | Yu-Chieh Su 蘇郁傑 |
| 指導教授: | 楊家驤(Chia-Hsiang Yang) |
| 關鍵字: | 稀疏碼多工存取,低密度奇偶檢查碼,迭代式偵測與解碼,5G無線通訊,CMOS數位積體電路, Sparse code multiple access (SCMA),Low-density parity-check (LDPC),iterative detection-and-decoding (IDD),Fifth-generation (5G) communication,CMOS digital integrated circuits, |
| 出版年 : | 2018 |
| 學位: | 碩士 |
| 摘要: | 稀疏碼多工存取技術(Sparse code multiple access, SCMA)是一種非正交多工存取技術,具有低傳輸延遲與高頻譜效率之優點,將用於5G通訊系統之大規模機器通信(mMTC)場景。以往研究中,稀疏碼多工存取多以最大後驗機率演算法進行多使用者偵測,但由於其運算複雜度過高,目前為止尚無硬體實現結果。本論文提出一具有高吞吐率之稀疏碼多用戶偵測方法,透過最小均方誤差平行式干擾消除演算法實現訊息傳遞,大幅降低稀疏碼多工存取所需之計算複雜度,在16QAM之8頻帶與12使用者之稀疏碼多工存取系統中,可有效降低96.3%之實數乘法運算。所提出之稀疏碼多工存取偵測器與低密度奇偶碼(low-density parity-check, LDPC)解碼器結合為一基頻接收機,可支援不同稀疏碼多重使用者設定。本論文所提出之稀疏碼多工存取偵測器與低密度奇偶檢查碼解碼器可進行軟式訊息交換,且訊息交換介面可同時存取偵測器與解碼器所需之軟式資訊,可提高硬體效率至100%,透過迭代式偵測與解碼可提升錯誤效能約3dB。接收機以40nm製程實現,可支援以QPSK或16QAM調變之4頻帶與6使用者以及8頻帶與12使用者之稀疏碼多工存取系統。晶片總邏輯閘數量約為10.9M,核心面積為3.382x3.382mm2。在0.9V電壓下之功耗為813mW,並達到最高吞吐率2.069Gb/s。 Sparse code multiple access (SCMA) is one of the most promising solutions among non-orthogonal multiple access (NOMA) technologies for the growing demand of massive machine type communications (mMTC), which is essential for the fifth-generation (5G) system. However, the complexity for SCMA detection is extremely high and no hardware implementation has been proposed in the open literature. In this thesis, a high-throughput, low-complexity minimum mean-square error with parallel interference cancellation (MMSE-PIC) detection for multiuser SCMA is proposed to reduce the computational complexity. A 96.3% complexity reduction is achieved for a 16QAM SCMA system with 8 frequency bands and 12 users (i.e., a 16QAM 8x12 SCMA system). The SCMA detector is reconfigurable to realize both the MMSE-PIC algorithm and MMSE-PIC-based message-passing algorithm (MPA). It is able to support both 4x6 and 8x12 SCMA systems with QPSK and 16QAM modulations. The proposed SCMA detector is integrated into a low-density parity-check (LDPC)-coded iterative detection and decoding (IDD) receiver. The interface between the SCMA detector and the LDPC decoder is properly designed to avoid data collision with a minimized latency and a 100% hardware utilization. The IDD receiver achieves a 3dB-gain compared to the non-IDD counterpart. Fabricated in a 40nm CMOS technology, the chip integrates 10.9M logic gates in area of 3.382x3.382mm2 and achieves a maximum throughput of 2.069 Gb/s. It dissipates 813mW at 200MHz from a 0.9V supply. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/69804 |
| DOI: | 10.6342/NTU201800672 |
| 全文授權: | 有償授權 |
| 顯示於系所單位: | 電子工程學研究所 |
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