應用於5G無線系統之毫米波65奈米CMOS混頻器及高線性度分佈式衍生疊加架構0.18毫米CMOS混頻器研究

Abstract

本論文主要分成兩部分，在第一部分提出了一個以65 nm CMOS製程設計的38 GHz次諧波升頻混頻器，其中設計頻段為未來5G可行通訊頻段(38 GHz)。此次諧波混頻器在38 GHz射頻(RF)頻率、5 GHz基頻(IF)頻率以及5 dBm的本地振盪源(LO)之下，能夠提供5.3±1.2 dB之增益、-10 dBm的輸出1 dB功率壓縮點(OP1dB)以及高於50 dB的兩倍LO到RF頻率之隔離度。 在第二部分設計了一個以0.18 μm CMOS製程製作的24 GHz高線性度之降頻混頻器。利用分佈式衍生疊加的架構，能夠比傳統的衍生疊加架構擁有更好的效果。本混波器在經過線性化之後，在24 GHz射頻(RF)頻率以及5 dBm的本地振盪源(LO)之下，本混頻器能夠提供-4 dB之增益以及23 dBm之三階輸入截止點(IIP3)，此三階輸入截止點為本頻段中所有已發表的CMOS線性化混頻器測試結果之中最好的。

There are many researches on millimeter-wave frond-end circuits for developing 5G wireless systems in recent years. The demands of high-speed internet and the shortage of the bandwidth have motivated the designers to explore millimeter wave (mm-wave) frequency with broader bandwidth for 5G cellular applications. The thesis presents two design parts. In the first part, a 38 GHz sub-harmonic up-conversion mixer is designed and measured in 65 nm CMOS process. The frequency is at 38 GHz which is potential for 5G communication in the future. This sub-harmonic mixer provides 5.3±1.2 dB conversion gain with -10 dBm OP1dB, more than 50 dB 2*LO-to-RF isolation at RF frequency of 38 GHz and IF frequency of 5 GHz under 5 dBm LO pumping power. In the second part, a high linearity down-conversion mixer with distributed deriva-tive superposition (DS) linearization technique in 0.18 μm CMOS process at 24 GHz is designed and measured. With the linearization, the mixer provides an acceptable gain of about -4 dB and the third-order input intercept point (IIP3) of the proposed mixer is achieves 23 dBm which is the best measured result among the previously works in K-band.