40-GHz 分數型時脈產生器

Abstract

現今的無線通信更加注重高速率和寬頻帶的需要。在Ka波段的PLL，所有模塊裡傳統寬帶操作最關鍵的是VCO和除頻器，佔用大面積和高功耗。本論文提出了一個頻率範圍為20-40GHz的分數型時脈產生器。此電路包括帶隙參考、相位檢測器、環路濾波器、VCO和由四/五級串聯的2/3除頻器所構成的多模數除頻器，總共除頻範圍為20-40。 PLL晶片採用40nm CMOS技術製造，尺寸為1.92×0.88 mm2，分別從1.2 V，1.5 V，1 V和2.5 V電源消耗220 mA，46 mA，7 mA和4mA電源，總功耗為0.35W。相位噪聲在與載波1MHz偏移處測量為-100.4dBc / Hz，均方根抖動為400fs。為了選擇正確的輸出頻率，內建了兩種的頻段選擇機制，都可以選擇正確的VCO和頻帶。為了最小化抖動，我們可以通過不同的電荷幫浦電流來改變環路帶寬。

Nowadays, wireless communication gets more attention to the demand of high rate and wide band. In a Ka-band PLL, the traditional VCO and frequency divider are the most critical to the broadband operation among all modules and occupy large silicon area and high power consumption. This thesis presents a fractional-N phase-locked loop (PLL) with a tuning range of 20-40GHz. The frequency synthesizer includes bandgap reference, phase detector, loop filter, VCO, and multimodulus divider with four/five cascaded 2/3 dividers that give an overall divide range of 20~40 in TSMC 40-nm CMOS technology. The PLL chip is fabricated in a 40-nm CMOS technology, measures 1.92×0.88 mm^2, and consumes 220 mA, 46 mA, 7 mA, and 4mA from a 1.2 V, 1.5 V, 1 V, and 2.5 V power supply, respectively, for a total power consumption of 0.35 W. The phase noise is measured to be -100.4dBc/Hz at 1 MHz offset from the carrier and root-mean-square jitter is 400fs. To choose the correct output frequency, two type of band selection mechanism are build and both can choose the right VCO and frequency band. To minimize the jitter, we can change loop bandwidth by different charge bump current.