請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66831完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 王暉(Huei Wang) | |
| dc.contributor.author | Bo-Ze Lu | en |
| dc.contributor.author | 呂柏澤 | zh_TW |
| dc.date.accessioned | 2021-06-17T01:09:07Z | - |
| dc.date.available | 2025-02-04 | |
| dc.date.copyright | 2020-02-04 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-01-20 | |
| dc.identifier.citation | [1] A. Wootten and A. R. Thompson, 'The Atacama large millimeter/submillimeter array,' in Proceedings of the IEEE, vol. 97, no. 8, pp. 1463-1471, Aug. 2009.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66831 | - |
| dc.description.abstract | 本論文包含三個部分。第一部分是應用於下個世代的無線電天文接收機的K頻段極低功耗的低雜訊放大器，使用65奈米金氧半場效電晶體製程設計。第二部分是應用於無線電射頻天文接收機的W頻段功率放大器，使用0.1微米砷化鎵假型高速場效電機體(pHEMT)製程設計。最後一部分是應用於毫米波第五代無線通訊系統的28十億赫茲(GHz)功率放大器，使用90奈米金氧半場效電晶體製程設計。
論文的第一部分呈現了一個使用65奈米CMOS的K頻段極低功耗低雜訊放大器。此電路使用了閘源極變壓器回授技術來同時達到阻抗和雜訊匹配，單端中和技術也被應用在這個電路。量測結果顯示本文提出的低雜訊放大器在22.5 GHz的頻率下有19.1 dB的小訊號增益和2.8 GHz的3 dB頻寬，且在22.5 GHz的頻率有3.6 dB的雜訊指數在有限的0.99 mW的功耗下。 在第二部分，提出了一個使用0.1微米砷化鎵假型高速場效電晶體製程的W頻段功率放大器。為了提升放大器的頻寬，輸出網路使用了兩段式匹配網路。量測結果顯示此功率放大器在82GHz的頻率有11.5-dB 的小訊號增益和15 GHz的3-dB增益頻寬從78-93 GHz，也提供了19.6 dBm的輸出飽和功率、18.2 dBm的輸出功率的增益1dB壓縮點(OP1dB)和12.8%的峰值功率附加效率(PAEpeak)。 最後一部分，提出了一個使用90奈米金氧半場效電晶體製程設計28 GHz F類功率放大器。此功率放大器是一個差動放大器的架構，且單端使用共源極電晶體。諧波調整的網路被建構在輸出端來提升功率效率。此外，本文也提出一個偏壓選擇方法來最佳化電路的線性度和功率退回(power back off)效率。量測結果顯示本文提出的功率放大器在28 GHz的頻率下有12.0 dB的小訊號增益和7.4 GHz的3 dB頻寬；此電路在28 GHz的頻率下也提供了14.9 dBm的輸出飽和功率和43.8%的峰值功率附加效率，還得到14.0 dBm的輸出功率的增益1dB壓縮點，其輸出功率下的功率附加效率也達到42%。在調變量測使用64-QAM的信號下，此功率放大器也達到了2.1/4.2 Gbit/s的資料傳輸速度、10.6/8.1 dBm的平均輸出功率和29.5/22.6%的平均功率附加效率，且方均根的錯誤向量大小(EVM)小於-25 dB。 | zh_TW |
| dc.description.abstract | This thesis consists of three parts. The first part is a K-band ultra-low-power low noise amplifier fabricated in 65-nm CMOS process for next-generation radio astronomical receivers. Another presents a W-band power amplifier fabricated in 0.1-μm GaAs pHEMT process for wideband radio astronomical receiver. The other describes a 28-GHz high linearity and high efficiency power amplifier fabricated in 90-nm CMOS process for fifth-generation wireless systems.
In the first part, an ultra-low-power K-band low noise amplifier (LNA) fabricated in 65-nm CMOS technology is presented. A gate-source transformer-feedback technique is utilized for simultaneous noise and input impedance matching. In order to achieve high gain with limited dc power consumption (PDC), a single-ended neutralization technique is applied to the circuit. The proposed K-band LNA achieves a 19.1-dB small signal gain with 2.8-GHz 3-dB bandwidth (21.2-24 GHz) and a noise figure of 3.6 dB with only 0.99-mW PDC at 22.5 GHz. In the second part, a monolithic W-band power amplifier (PA) in 0.1-μm depletion mode (D-mode) Gallium Arsenide (GaAs) pHEMT process is presented. In order to increase the bandwidth, two-section network for output is utilized. The proposed PA achieves a 11.5-dB small signal gain with 15-GHz 3-dB bandwidth (78-93 GHz), a saturated output power (Psat) of 19.6 dBm, an output 1-dB compression point (OP1dB) of 18.2 dBm, and a maximum power added efficiency (PAEpeak) of 12.8% at 82 GHz. In the last part, a 28-GHz Class-F power amplifier (PA) fabricated in 90-nm CMOS technology is presented. This PA is a differential pair amplifier topology consisted of two common-source (CS) cells. The harmonic-tuned network is constructed at output to enhance the power efficiency. Besides, the bias selection is discussed to optimize the linearity, also to increase the power back-off efficiency. The proposed Class-F PA achieves a 12-dB small-signal gain with 7.4-GHz 3-dB bandwidth (25.1-32.5 GHz), 14.9-dBm Psat with 43.8% peak PAE, and 14.0-dBm OP1dB with 42.0% PAE1dB at 28 GHz. With the single-carrier 64-QAM signal, this PA achieves 2.1/4.2 Gbit/s data rate, 10.6-dBm/8.1-dBm average output power, and 29.5%/22.6% average PAE, while maintaining root-mean-square (rms) error vector magnitude (EVM) better than -25 dB. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T01:09:07Z (GMT). No. of bitstreams: 1 ntu-109-R06942085-1.pdf: 8266327 bytes, checksum: 370cd502f9594671f15c753318432fe2 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | CONTENTS
口試委員會審定書 # 誌謝 ii 中文摘要 iv ABSTRACT vi CONTENTS viii LIST OF FIGURES xi LIST OF TABLES xix Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.1.1 Atacama Large Millimeter/submillimeter Array 1 1.1.2 Next-generation Radio Astronomical Application 2 1.1.3 Fifth Generation Communications 2 1.2 Literature Survey 4 1.2.1 Ultra-low-power Low Noise Amplifier in CMOS Technology 4 1.2.2 W-band Broadband Power amplifier in GaAs pHEMT Process 6 1.2.3 Millimeter-wave Linear and Efficient Power Amplifier 8 1.3 Contributions 10 1.3.1 K-band CMOS LNA for Next Generation Radio Astronomical Application 10 1.3.2 W-band GaAs pHEMT PA for Radio Astronomical Receiver 10 1.3.3 28-GHz Linear and Efficient CMOS PA for 5G communications 11 1.4 Thesis Organization 12 Chapter 2 The Design of Ultra-Low-Power K-band Low Noise Amplifier in 65-nm CMOS Technology 13 2.1 Introduction 13 2.2 The Design of K-band LNA 16 2.2.1 Biasing Selection and Device Selection 16 2.2.2 Quality Factor of Inductors and 3D-Inductors 23 2.2.3 The Design of First Stage 29 2.2.4 The Design of Second Stage 33 2.2.5 Circuit Schematic and Post-layout simulations 37 2.3 Experimental Results 44 2.4 Summary 49 Chapter 3 The Design of W-band Power Amplifier in 0.1-μm D-mode GaAs pHEMT Process 51 3.1 Introduction 51 3.2 Circuit Design 54 3.2.1 MMIC Process Characteristics 54 3.2.2 Block Diagram and Power Budget 55 3.2.3 Quadrature Power Combiners / Splitters 56 3.2.4 The Design of Single-ended Amplifiers 62 3.2.5 Circuit Schematic and Post-Layout Simulations 73 3.3 Experimental Results 78 3.4 Summary 83 Chapter 4 A 28-GHz High Linearity and High Efficiency Class-F Power Amplifier in 90-nm CMOS Technology for Multi-Gb/s 5G Communications 84 4.1 Introduction 84 4.2 The Demand of the High-order Complex-modulation Schemes 86 4.3 Basic Theory of Power Amplifier Operation 93 4.3.1 Basic Classes of Power Amplifier Operation [51]-[53] 93 4.3.2 Class-F Theory [52] 95 4.4 Circuit Design 99 4.4.1 Block Diagram and Power Budget 99 4.4.2 Device and Bias Selection 100 4.4.3 Neutralized Technique 104 4.4.4 Load-pull Simulation for Class-F operation 107 4.4.5 Harmonic-tuned Output Network 110 4.4.6 Circuit Schematic and Post-layout simulations 116 4.4.7 Stability Check of the Circuit 121 4.5 Experimental Results 125 4.5.1 S-parameters and Large-signal CW Performances 126 4.5.2 Digital Modulation 129 4.6 Summary 133 Chapter 5 Conclusion 136 REFERENCE 138 LIST OF FIGURES Fig. 2.1 dc-IV curve of the transistor with 48-μm total gate width. 16 Fig. 2.2 Gm of the transistor with 48-μm total gate width in different VG. 17 Fig. 2.3 Drain Current of the transistor with 48-μm total gate width in different VG. 17 Fig. 2.4 MSG, NFmin of the transistor with 48-μm total gate width in different VG. 18 Fig. 2.5 MSG/MAG and stability factor in different device sizes. 19 Fig. 2.6 Minimum noise figure in different device sizes. 19 Fig. 2.7 MSG and NFmin of the transistor with 48-μm total gate width under a constant PDC with different VG. 21 Fig. 2.8 Equivalent circuit of an inductor and a capacitor. 23 Fig. 2.9 Schematic of a LC series circuit. 24 Fig. 2.10 Schematic of a LC parallel circuit. 25 Fig. 2.11 On-chip model of a spiral inductor. 26 Fig. 2.12 (a) EM model of an 0.5nH inductor in 65 nm CMOS process and (b) Q factor in different space (S). 27 Fig. 2.13 2-nH 3D-solenoid inductors: (a) two metals completely overlap and (b) two metals are offset. 28 Fig. 2.14 Simulated inductance and Q factor of two layouts of the 3D inductors. 28 Fig. 2.15 Small signal equivalent circuit of a common source transistor with an inductive degeneration at source terminal and a series inductor at gate terminal. 30 Fig. 2.16 Conjugate input impedance and optimal noise impedance in Smith chart with (a) inductive degeneration and (b) both inductive degeneration and gate inductor. 30 Fig. 2.17 Topology of gate-source transformer-feedback technique and its small signal equivalent circuit. 31 Fig. 2.18 Conjugate input impedance and optimal noise impedance in Smith chart with (a) gate-source transformer-feedback technique and (b) both gate-source transformer-feedback technique and a series capacitor. 32 Fig. 2.19 EM models of the input network. 32 Fig. 2.20 Circuit schematic of the second stage of the LNA. 33 Fig. 2.21 Matching network between the second stage and the third stage. 35 Fig. 2.22 (a) The circuit schematic of the positive-feedback neutralization technique. (b) MSG/MAG and stability factor of the device with 30-μm total gate width using the positive-feedback capacitor. (VGS = 0.42 V, VDS = 0.30 V). 35 Fig. 2.23 EM models of the transformer and neutralized technique. 36 Fig. 2.24 Complete circuit schematic of the proposed K-band LNA. 37 Fig. 2.25 Simulated S-parameters of the proposed K-band LNA. 38 Fig. 2.26 Simulated noise figure of the proposed K-band LNA. 39 Fig. 2.27 Loss distribution of the proposed LNA. 39 Fig. 2.28 Simulated large-signal performances of the proposed K-band LNA. 40 Fig. 2.29 Two-tone simulations of the proposed K-band LNA. 40 Fig. 2.30 Chip layout of the proposed K-band PA. 42 Fig. 2.31 Stability factor of the proposed LNA. 42 Fig. 2.32 The simulation of inter-stage stability mapping circles. 43 Fig. 2.33 The simulation of inter-stage stability mapping circles. 43 Fig. 2.34 Die micrograph in 65-nm bulk CMOS process. 44 Fig. 2.35 Measured and simulated S-parameters of the proposed K-band LNA. 45 Fig. 2.36 Measured and simulated noise figure of the proposed K-band LNA. 45 Fig. 2.37 Geometry of the MIM capacitor and its equivalent models. 46 Fig. 2.38 The MIM capacitor of 3.0 pF and its equivalent models. 47 Fig. 2.39 Schematic diagram of the parasitic effects in implementation. 47 Fig. 2.40 Measured and simulated S-parameters after considering the parasitic effects of the MIM capacitor. 47 Fig. 2.41 Measured and simulated noise figure after considering the parasitic effects of the MIM capacitor. 48 Fig. 2.42 (a) Measured and simulated large signal performances and (b) two-tone simulation and measurement of the proposed LNA. (fcenter:22.5 GHz, spacing: 20 MHz) 48 Fig. 3.1 Block diagram of radio astronomical receiver front-end system. 52 Fig. 3.2 The diagram of the 0.1-μm D-mode GaAs pHEMT process. 54 Fig. 3.3 Block diagram and power budget of the PA. 55 Fig. 3.4 The structure of Wilkinson power divider with a 90o delay line. 57 Fig. 3.5 The frequency response of Wilkinson power divider. 57 Fig. 3.6 The phase difference between port 2 and port 3 of Wilkinson power divider. 57 Fig. 3.7 The structure and Layout of the employed Lange coupler. 59 Fig. 3.8 Input return loss of the isolated terminal. 59 Fig. 3.9 The frequency response of the Lange coupler. 59 Fig. 3.10 The phase difference between port 2 and port 3 of the Lange coupler. 60 Fig. 3.11 Input impedances of port 2 and port 3. 60 Fig. 3.12 The dc-IV curves of the 2 fingers × 75 μm device and selected bias point (VD =3V, VG =-0.4V). 62 Fig. 3.13 Transconductance (gm) of the 2 fingers × 75 μm device. 63 Fig. 3.14 MSG/MAG of the 2 fingers × 75 μm device in different VD bias. 63 Fig. 3.15 Simulated MAG/MSG of the power-stage transistors. 65 Fig. 3.16 Simulated stability factor of the power-stage transistors. 65 Fig. 3.17 Load-pull simulation of the 2 fingers × 75 μm device at 79 GHz. 66 Fig. 3.18 Load-pull simulation of the 2 fingers × 75 μm device at 86 GHz. 67 Fig. 3.19 Load-pull simulation of the 2 fingers × 75 μm device at 94 GHz. 67 Fig. 3.20 The simulated large-signal of the power-stage with ideal impedance matching. 68 Fig. 3.21 1-dB compression load-pull simulation of 2 fingers × 75 μm device. 69 Fig. 3.22 1-dB compression load-pull simulation of 2 fingers × 50 μm device. 70 Fig. 3.23 The simulated large-signal of the driver stage with ideal impedance matching. 70 Fig. 3.24 The Zopt of 79 GHz, 86 GHz and 94 GHz in Smith chart. 72 Fig. 3.25 The output matching procedures at 86 GHz. 72 Fig. 3.26 Single-ended circuit schematic of the proposed PA. 73 Fig. 3.27 Block diagram of the proposed PA. 73 Fig. 3.28 The simulated S-parameters of the single-ended and balanced amplifier. 74 Fig. 3.29 The simulated large signal performances of the proposed W-band PA 75 Fig. 3.30 Chip layout of the proposed W-band PA. 75 Fig. 3.31 Stability factor of the proposed W-band PA. 76 Fig. 3.32 The simulation of inter-stage stability mapping circles. 77 Fig. 3.33 The simulation of inter-stage stability mapping circles. 77 Fig. 3.34 Chip photograph of the proposed W-band PA 78 Fig. 3.35 Large-signal power sweep measurement setup. 79 Fig. 3.36 off-chip bias circuit and PCB layout of the proposed PA. 80 Fig. 3.37 Measured and simulated S-parameters of the W-band PA 81 Fig. 3.38 Measured and simulated power performance of the proposed PA at 86 GHz. 82 Fig. 3.39 Measured and simulated OP1dB, Psat and PAE of the proposed PA over different frequencies. 82 Fig. 4.1 Constellation diagram of the BPSK 87 Fig. 4.2 Block diagram of the IQ modulator. 88 Fig. 4.3 Block diagram of the IQ demodulator. 88 Fig. 4.4 Constellation diagram of the QPSK. 88 Fig. 4.5 Constellation diagram of the 16-QAM. 89 Fig. 4.6 Constellation diagram of the 64-QAM. 91 Fig. 4.7 Primary BER map versus Received signal power level. 92 Fig. 4.8 Voltage and current waveforms and dissipated power. 94 Fig. 4.9 Voltage and current waveforms of the Class-F operation. 98 Fig. 4.10 The block diagram and initial power budget of the proposed PA. 99 Fig. 4.11 The dc-IV curve with the device of 256-μm total gate width. 100 Fig. 4.12 ID and gm versus different VGS with the device of 256-μm total gate width. 101 Fig. 4.13 The dc drain currents of VGS with different bias conditions. 103 Fig. 4.14 The PAE of VGS with different bias conditions. 103 Fig. 4.15 Small signal equivalent circuit of a differential pair. 104 Fig. 4.16 Small signal equivalent circuit of the differential pair with neutralized technique in differential mode. 106 Fig. 4.17 The simulated K and maximum gain of a differential pair with the device of 256-μm total gate width as a function of CN, and the layout of output stage cell. 106 Fig. 4.18 The setup of load-pull simulation for Class-F operation. 107 Fig. 4.19 Load-pull simulation with Class-B operation. 108 Fig. 4.20 Load-pull simulation with Class-F operation. 108 Fig. 4.21 The simulated large-signal CW performance of Class-B and Class-F operations with ideal source and load impedances. 109 Fig. 4.22 Circuit schematic and EM model of the proposed harmonic-tuned output network. 110 Fig. 4.23 The equivalent half circuit of the harmonic-tuned output network. 111 Fig. 4.24 The equivalent half circuit of fundamental frequency. 111 Fig. 4.25 The equivalent half circuit of 2nd harmonic frequency. 112 Fig. 4.26 The equivalent half circuit of 3rd harmonic frequency. 113 Fig. 4.27 The ZCF of fundamental, 2nd and 3rd harmonics. 113 Fig. 4.28 The setup for checking the S-parameters of the output network. 114 Fig. 4.29 The simulated insertion loss and I/O return losses of the EM output network. 114 Fig. 4.30 The simulated insertion loss and I/O return losses of the EM input network. 115 Fig. 4.31 Loss distribution of the proposed PA. 115 Fig. 4.32 Complete circuit schematic of the proposed Class-F PA. 117 Fig. 4.33 Simulated dc drain current and PAE with different VG at different output power levels. 118 Fig. 4.34 Simulated AM-AM and AM-PM distortions with different VG at different output power levels. 118 Fig. 4.35 Simulated S-parameters of the proposed Class-F PA. 119 Fig. 4.36 Simulated large signal CW performances of the proposed Class-F PA. 119 Fig. 4.37 Simulated large signal CW performances of the proposed Class-F PA at different frequency from 25 GHz to 32 GHz. 120 Fig. 4.38 Simulated drain voltage and current waveforms at node A. 120 Fig. 4.39 Chip layout of the proposed Class-F PA. 121 Fig. 4.40 Small signal schematic of a neutralized nNOS differential pair in common mode. 122 Fig. 4.41 Schematic representation of the common mode source and input impedance. 123 Fig. 4.42 Common mode stability check with and without the bias resistor at gate terminal. 124 Fig. 4.43 Stability factor of the proposed PA in common mode with swept RBias,CM. 124 Fig. 4.44 Stability factor of the proposed PA in differential mode. 124 Fig. 4.45 Die micrograph in 90-nm bulk CMOS process. 125 Fig. 4.46 Simulated and measured S-parameters of the proposed Class-F PA. 126 Fig. 4.47 Simulated and measured large signal CW performances of the proposed Class-F PA. 127 Fig. 4.48 Measured large signal CW performances of the proposed Class-F PA at different frequencies from 25 GHz to 32 GHz. 127 Fig. 4.49 Measured and re-simulation S-parameters of the proposed PA. 128 Fig. 4.50 Measured and simulated dc drain current in different power levels. 128 Fig. 4.51 The measured modulation results with the single carrier 64-QAM signals of 350/700 Msymbol/s. 130 Fig. 4.52 The measured modulation results with the single carrier 256-QAM signals of 100/200 Msymbol/s. 130 Fig. 4.53 Measured modulation results with the OFDM 256-QAM signals of the 350/750 MHz bandwidth. 131 Fig. 4.54 Measured (a) EVM and (b) PAE versus average output power of this work at 28 GHz. 132 LIST OF TABLES Table 1.1 Performance summary of the published low-power CMOS LNAs. 5 Table 1.2 Performance summary of the published W-band broadband PA. 7 Table 1.3 Performance summary of the published mm-Wave CMOS PA. 9 Table 1.4 Modulation performance summary of the published mm-Wave CMOS PA. 9 Table 2.1 Performances summary by using the forward body-bias technique. 14 Table 2.2 Specifications of the K-band CMOS LNA. 15 Table 2.3 Trade-off study of the device size selection for LNA. 20 Table 2.4 MSG and NFmin for different device sizes with the best bias point at 24 GHz. 22 Table 2.5 ZS and Zopt of the different device sizes. 22 Table 2.6 The simulated dc condition of each stage of the K-band LNA. 38 Table 2.7 Performance with VDS biased at 0.3 V and 1 V. 41 Table 2.8 Comparison of published state-of-the-art ultra-low-power K-band CMOS low noise amplifiers 50 Table 3.1 Specifications of the W-band GaAs pHEMT PA. 53 Table 3.2 The width of double-metal TLs in different characteristic impedance. 56 Table 3.3 The size of the employed Lange coupler. 58 Table 3.4 Comparison of two type of quadrature power combiners/splitters. 61 Table 3.5 Simulated MSG/MAG and stability factor of each device size. 64 Table 3.6 Summary of load-pull simulation of the 2 fingers × 75 μm device. 68 Table 3.7 Summary of load-pull simulation for the driver-stage transistors. 71 Table 3.8 The simulated dc condition of each stage of the W-band PA 74 Table 3.9 The measured dc condition of each stage of the W-band PA 80 Table 3.10 Comparison of published W-band GaAs pHEMT broadband power amplifiers. 83 Table 4.1 The bits/symbol, PAPR, and amplitude/phase tolerances of different modulation schemes. 91 Table 4.2 Ideal efficiency and gain in different classes operation. 94 Table 4.3 Load-pull simulations of different conditions of the same device size. 101 Table 4.4 The load-pull simulations of VGS with different bias conditions. 103 Table 4.5 Comparison of the performances with Class-B and Class-F operations. 109 Table 4.6 Modulation measured results with different modulation schemes. 132 Table 4.7 Comparison of the published 5G mm-Wave CMOS PAs. 134 Table 4.8 Modulation comparison of the published 5G mm-Wave CMOS PAs. 135 | |
| dc.language.iso | en | |
| dc.title | 天文接收機之放大器和第五代行動通訊之功率放大器的研究 | zh_TW |
| dc.title | Research of Amplifier for Astronomical Receiver and Power Amplifier for 5G Mobile Communications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃天偉(Tian-Wei Huang),林坤佑(Kun-You Lin),蔡作敏(Zuo-Min Tsai),章朝盛(Chau-Ching Chiong) | |
| dc.subject.keyword | 互補式金屬氧化物半導體,砷化鎵,高速場效電晶體,功率放大器,低雜訊放大器,W頻段,K頻段, | zh_TW |
| dc.subject.keyword | CMOS,GaAs,Power amplifier,Low noise amplifier,W-band,K-band, | en |
| dc.relation.page | 143 | |
| dc.identifier.doi | 10.6342/NTU202000206 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2020-01-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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