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Title: | 具量化雜訊抑制之全數位小數頻率合成器 A Quantization Noise Suppression Technique for All-Digital Fractional-N PLLs |
Authors: | Sung-Lin Tsai 蔡松林 |
Advisor: | 林宗賢(Tsung-Hsien Lin) |
Keyword: | 全數位小數頻率合成器,量化雜訊,小數突波,時間數位轉換器,鎖相迴路, All-digital Fractional-N Frequency Synthesizer,Quantization Noise,Fractional Spur,Time-to-Digital Converter,Phase-Locked Loop, |
Publication Year : | 2012 |
Degree: | 碩士 |
Abstract: | 本篇論文實現了一個量化雜訊抑制的全數位小數型鎖相迴路。針對三角積分調變器所造成的量化雜訊與小數突波進行改善。此技巧透過產生新的調變路徑,量化步階與調變頻率皆可以獨自設計而不受迴路參數影響。量化雜訊能量可以因而減少且集中在高頻。此外藉由增加調變器的輸入並且在數位迴路前補償的方式,小數突波也因此被移動到高頻。因此,量化雜訊與小數突波可被迴路更有效率的抑制。
此量化雜訊抑制技巧實現於一個36億赫茲頻帶的全數位鎖相迴路。使用台積電90奈米製程,整個系統操作在1.2-V共花費9.25 mA電流。在36億赫茲下,所量測到的參考突波為 -70 dBc。相位雜訊於10-MHz頻率誤差下從 -90 dBc/Hz改善成 -121 dBc/Hz。小數突波也被抑制了5 dB。 This thesis presents a quantization noise suppression technique for all-digital fractional-N PLL to address the quantization noise and fractional spur issues from the ΔΣ modulator. The proposed technique builds a new modulation path that allows the quantization step and modulation frequency to be designed independently and not limited by the loop parameters. The quantization noise power is thus reduced and shifted to higher frequency offset. In addition, by increasing modulator input value and compensating later in digital domain, the fractional spur is also shifted to higher frequency offset. Therefore, both quantization noise and fractional spur are filtered by the loop more effectively. The proposed technique is implemented in the design of a 3.6-GHz ADPLL. Fabricated in the TSMC 90-nm CMOS technology, the whole system dissipates 9.48 mA from a 1.2-V supply. At 3.6 GHz, the reference spur at 25 MHz offset is -70 dBc and the phase noise measured at 10-MHz offset is reduced from -90 dBc/Hz to -121 dBc/Hz. The fractional spur is also reduced by 5 dB. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64272 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
File | Size | Format | |
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ntu-101-1.pdf Restricted Access | 2.74 MB | Adobe PDF |
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