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標題: | 具有嚴格輸出電壓調控與自動波谷切換之一次側控制準諧振返馳式轉換器設計 Design of a Primary-Side-Control Quasi-Resonant Flyback Converter With Tight Output Voltage Regulation and Self-Calibrated Valley Switching |
作者: | Ping-Chun Hsieh 謝秉均 |
指導教授: | 陳秋麟(Chern-Lin Chen) |
關鍵字: | 返馳式轉換器,一次側控制,輸出電壓調控,準諧振,波谷切換, flyback converter,primary-side control,output voltage regulation,quasi-resonant,valley switching, |
出版年 : | 2013 |
學位: | 碩士 |
摘要: | 本篇論文針對一次側控制之準諧振返馳式轉換器提出可達成準確輸出電壓調控之一次側偵測電路與全自動之波谷切換技術。藉由追蹤輔助繞組的電壓斜率,控制晶片可使用簡單的類比電路,在二次側電感之電流降至某一固定值的瞬間取得輸出電壓資訊,進而減少輸入線電壓與輸出負載對於輸出電壓的影響。為了方便以類比方式偵測電壓的斜率值,將輔助繞組的回授電壓與一固定斜率之斜坡電壓相加,使偵測電路改為追蹤零斜率之瞬間。
本文所提出的自動波谷切換技術採用擾動觀察法來偵測諧振之波谷,不需要任何額外的離散元件即可達成波谷切換。除此之外,為了避免在較輕載時產生嚴重的電磁干擾,採用波谷省略方式來降低切換頻率,使得功率電晶體在第一個之後的汲極電壓波谷開始導通。考慮到電壓偵測接腳存在一定程度的雜散電容而使得諧振波谷點產生延遲,本文也提出可測量與修正RC延遲之電路來校正此非理想效應。 採用世界先進0.5-um 5-V/40-V CMOS高低壓混合製程之電路模型,本文將所提出之電路技術整合在返馳式轉換器控制晶片中並進行全系統之模擬。針對本文所設計輸出電壓為6.2 V與額定功率5 W之一次側準諧振返馳式轉換器,模擬結果顯示在最高與最低之輸入線電壓下,從10%負載到全載的範圍中輸出電壓之變動量皆不大於0.8%。同時,若針對不同準諧振頻率、負載電流、與雜散電容進行模擬,所提出的波谷切換電路皆可準確使功率電晶體導通在汲極電壓之最低點。 This thesis presents methods and circuits to achieve tight output voltage regulation and self-calibrated valley switching for primary-side-control quasi-resonant (QR) flyback converters. By tracking the slope of auxiliary winding voltage, the controller retrieves the output voltage information at a fixed diode current with a simple analog method, and it thus suppresses the load and line effects on the output voltage. To sense the voltage slope, a compensating ramp is applied to the feedback voltage and the sensing circuit detects the zero-slope point instead. The proposed self-calibrated valley switching circuit is based on perturb and observe (P&O) algorithm to automatically detect the QR valley, and no extra off-chip component is required. Besides, to avoid EMI problem, the valley skipping method is employed to switch on the power MOSFET at later QR valley rather than the first one to lower switching frequency under light load condition. Considering the valley-point mismatch effect due to parasitic capacitance, RC delay estimation and tangency extraction circuit are also developed to correct the non-ideal effect. A primary-side flyback controller incorporating the two proposed circuits has been designed and simulated using the SPICE model for VIS 0.5-m 5-V/40-V high-voltage CMOS process. Simulation results from a 6.2-V/5-W QR flyback converter exhibit 0.8% output voltage variation from 10% load to full load considering both low and high line voltages. Meanwhile, simulations conducted under different QR frequencies, various load conditions, and different amounts of parasitic capacitance confirm the validity of the proposed valley switching technique. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62433 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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ntu-102-1.pdf 目前未授權公開取用 | 3.4 MB | Adobe PDF |
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