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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Chen Hsin-Shu) | |
| dc.contributor.author | Cheng-Hsueh Tsai | en |
| dc.contributor.author | 蔡承學 | zh_TW |
| dc.date.accessioned | 2021-06-16T13:32:11Z | - |
| dc.date.available | 2015-08-23 | |
| dc.date.copyright | 2013-08-23 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-07-19 | |
| dc.identifier.citation | [1] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. Wiley-IEEE Press, 1995
[2] Zhiheng Cao; Shouli Yan; Yunchu Li, 'A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 μm CMOS,' Solid-State Circuits, IEEE Journal of , vol.44, no.3, pp.862,873, March 2009 [3] Hegong Wei; Chi-Hang Chan; U-Fat Chio; Sai-Weng Sin; U Seng-Pan; Martins, R.; Maloberti, F., 'A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS,' Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International , vol., no., pp.188,190, 20-24 Feb. 2011 [4] Doris, K.; Janssen, E.; Nani, C.; Zanikopoulos, A.; Van Der Weide, G., 'A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist,' Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International , vol., no., pp.180,182, 20-24 Feb. 2011 [5] Alpman, E.; Lakdawala, H.; Carley, L.R.; Soumyanath, K., 'A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS,' Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International , vol., no., pp.76,77,77a, 8-12 Feb. 2009 [6] Chen, S.-W.M.; Brodersen, R.W., 'A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS,' Solid-State Circuits, IEEE Journal of , vol.41, no.12, pp.2669,2680, Dec. 2006 [7] Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin, 'A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,' Solid-State Circuits, IEEE Journal of , vol.45, no.4, pp.731,740, April 2010 [8] Tao Jiang; Wing Liu; Zhong, F.Y.; Zhong, C.; Kangmin Hu; Chiang, P.Y., 'A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS,' Solid-State Circuits, IEEE Journal of , vol.47, no.10, pp.2444,2453, Oct. 2012 [9] Furuta, M.; Nozawa, M.; Itakura, T., 'A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS,' Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.382,383, 7-11 Feb. 2010 [10] Young-Deuk Jeon; Young-Kyun Cho; Jae-Won Nam; Kwi-Dong Kim; Woo-Yol Lee; Kuk-Tae Hong; Jong-Kee Kwon, 'A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS,' Custom Integrated Circuits Conference (CICC), 2010 IEEE , vol., no., pp.1,4, 19-22 Sept. 2010 [11] Sai-Weng Sin; Li Ding; Yan Zhu; He-Gong Wei; Chi-Hang Chan; U-Fat Chio; Seng-Pan U; Martins, R.P.; Maloberti, F., 'An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H,' ESSCIRC, 2010 Proceedings of the , vol., no., pp.218,221, 14-16 Sept. 2010 [12] Yan Zhu; Chi-Hang Chan; U-Fat Chio; Sai-Weng Sin; Seng-Pan U; Martins, R.P.; Maloberti, F., 'A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS,' Solid-State Circuits, IEEE Journal of , vol.45, no.6, pp.1111,1121, June 2010 [13] Chien-Hung Kuo; Cheng-En Hsieh, 'A high energy-efficiency SAR ADC based on partial floating capacitor switching technique,' ESSCIRC (ESSCIRC), 2011 Proceedings of the , vol., no., pp.475,478, 12-16 Sept. 2011 [14] Wicht, B.; Nirschl, T.; Schmitt-Landsiedel, D., 'Yield and speed optimization of a latch-type voltage sense amplifier,' Solid-State Circuits, IEEE Journal of , vol.39, no.7, pp.1148,1158, July 2004 [15] Kuttner, F., 'A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13μm CMOS,' Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International , vol.2, no., pp.136,137, 2002 [16] Hung-Yen Tai; Hung-Wei Chen; Hsin-Shu Chen, 'A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS,' VLSI Circuits (VLSIC), 2012 Symposium on , vol., no., pp.92,93, 13-15 June 2012 [17] Ying-Zu Lin; Soon-Jyh Chang; Yen-Ting Liu; Chun-Cheng Liu; Guan-Ying Huang; , 'An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count,' Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.57, no.8, pp.1829-1837, Aug. 2010 [18] J. Yang, T. L. Naing, and R. W. Brodersen, “A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing,” J. Solid-State Circuits, vol. 45, no. 8, pp. 1469-1478, Aug. 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62179 | - |
| dc.description.abstract | 以40奈米CMOS一般製程製作一個單通道六位元每秒八億次的兩段連續漸近式類比數位轉換器。使用源極隨耦器做為緩衝器，將六位元連續漸近式類比數位轉換器拆開成前後兩級，此設計可直接使用工作週期50%的時鐘信號，因而省去複雜的週期信號產生器。另外，準位平移技巧加快約30 %的轉換率；任意選擇權重之電容陣列可補償前後兩級比較器造成的電壓偏移誤差，因此可省去電壓偏移校正電路。
根據晶片量測結果，在800MS/s的轉換率下的DNL和INL分別為+0.50/-0.42 LSB 和+0.65/-0.51LSB。在輸入頻率為393.8MHz且在800MS/s的轉換率下時，SNDR和SFDR 分別為35.3dB和45.6dB。在1V的供應電壓和800MS/s的轉換率下的功率消耗為3.72mW，換算成FoM為98 fJ/c.s.。全部的晶片面積大小為0.36mm2，然而主動電路所占的面積只有0.009mm2。 | zh_TW |
| dc.description.abstract | A single-channel 6-bit 800MS/s two-step SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is fabricated in 40nm CMOS general–process technology. Using source follower as inter-stage residue amplifier, this work divides 6-bit SAR ADC into two stages for directly using external 50% duty clock. In other words, no duty cycle generator, which generates non-50% duty clock signal, is needed in this architecture. Proposed level-shift technique is used to accelerate ADC conversion rate by approximate 30%. Arbitrary weight capacitor array replaces calibration circuit to compensate errors caused by offset between comparators in the two stages.
According to measurement results, this prototype ADC exhibits DNL of +0.50/-0.42LSB and INL of +0.65/-0.51LSB at 800 MS/s. SNDR and SFDR are 35.3dB and 45.6dB at 800MS/s with 393.8MHz input frequency. The power consumption is 3.72mW at 1V supply voltage and at 800MS/s conversion rate. As a result, the FoM (Power/2ENOB/FS) is 98fJ/conversion-step. The whole chip including pads occupies 0.36mm2 while active area is only 0.009mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T13:32:11Z (GMT). No. of bitstreams: 1 ntu-102-R00943031-1.pdf: 6109720 bytes, checksum: cde4cb0216c918c8ed3d9c1f70eb5f8c (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | Contents
致謝 I 摘要 II Abstract III Contents IV List of Figures VIII List of Tables XII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converter 3 2.1 Introduction 3 2.2 Performance Metrics 3 2.2.1 Static Performance 3 2.2.2 Dynamic Performance 5 2.3 ADC Architectures 8 2.3.1 Flash ADC Architecture 8 2.3.2 Two-Step ADC Architecture 9 2.3.3 Successive-Approximation-Register ADC Architecture 11 2.3.4 Pipelined ADC Architecture 12 2.3.5 Continuous-Time Delta-Sigma ADC Architecture 13 2.4 Summary 15 Chapter 3 Proposed Two-Step SAR ADC Using Source Follower as Buffer 16 3.1 Introduction 16 3.2 Two-Step SAR ADC 18 3.2.1 Prior Work 1: Single-Channel Two-Step SAR ADC 18 3.2.2 Prior Work 2: Dual-Channel 10-Bit Two-Step SAR ADC 21 3.2.3 Prior Work 3 : Time-Interleaved 11-Bit Two-Step SAR ADC 25 3.2.4 Proposed Single-Channel Two-Step SAR ADC 26 3.3 Design Considerations of the Proposed Two-Step SAR ADC 32 3.3.1 Settling Time and Gain of Source Follower 32 3.3.2 Kickback Noise of Source Follower 37 3.3.3 Asynchronous Processing 39 3.3.4 Monotonic Capacitor Switching 40 3.3.5 Proposed Level-shift Technique 42 3.3.6 Gain Mismatch 44 3.3.7 Offset Mismatch and AWCA 44 3.3.8 Thermal Noise of DAC 47 3.4 Summary 47 Chapter 4 Circuit Implementation and Simulation Results 49 4.1 Introduction 49 4.2 Building Blocks and Circuit Implementation 49 4.2.1 Source Follower 50 4.2.2 Coarse and Fine AWCA 54 4.2.3 Comparator 57 4.2.4 Improved Sampling Circuit 62 4.2.5 SAR Controller 66 4.3 Overall ADC Simulation Results 69 4.3.1 Behavior Simulation 69 4.3.2 Transistor Level Simulation 70 4.4 Summary 73 Chapter 5 Measurement Results 74 5.1 Introduction 74 5.2 Floor Plan and Layout Design 74 5.3 PCB Design 76 5.4 Test Setup 79 5.5 Measurement Results 82 5.5.1 Static Performance 82 5.5.2 Dynamic Performance 83 5.6 Summary 85 Chapter 6 Conclusions 87 Bibliography 88 | |
| dc.language.iso | en | |
| dc.title | 一個單通道六位元每秒八億次取樣的兩段連續漸近式類比數位轉換器 | zh_TW |
| dc.title | A Single-Channel 6-bit 800MS/s Two-Step SAR ADC | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),蔡宗亨(Tsung-Heng Tsai) | |
| dc.subject.keyword | 連續漸近式類比數位轉換器, | zh_TW |
| dc.subject.keyword | SAR ADC,Two-Step, | en |
| dc.relation.page | 91 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-07-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-102-1.pdf 目前未授權公開取用 | 5.97 MB | Adobe PDF |
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