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Title: | 適用於802.11n之低密度同位檢查解碼器晶片設計 Chip Design of a Low Density Parity Check Decoder for IEEE 802.11n |
Authors: | Ho-Sheng Chuang 莊和昇 |
Advisor: | 陳少傑(Sao-Jie Chen) |
Co-Advisor: | 游竹(Chu Yu) |
Keyword: | 低密度同位檢查碼,收斂,最小和演算法,區塊式解碼器,提早處理,降低關鍵路徑, Low Density Parity Check (LDPC),Convergence,Min-Sum Algorithm,Block-serial Decoder,Early Process,Shorting Critical Path, |
Publication Year : | 2013 |
Degree: | 碩士 |
Abstract: | 早期受限於當時電腦計算能力不夠,使得這個演算法未受到應有的重視。然隨著電腦運算能力大幅成長,以及製程技術越來越先進。低密度同位檢查碼再度引起熱烈的討論。解碼器架構大致可分兩種:全平行(Fully-parallel)和部分平行(Partial-parallel)。其中部分平行又會因為平行度和平行方式的不同,又有一些類別。
在本論文中,我們採用部分平行區塊式架構進行設計低密度同位元檢查解碼器。為了改善Xiang學者所提出的架構,我們提出三個改良的方法:首先我們藉由重組處理和儲存的順序,縮短了解碼器的關鍵路徑(Critical Path),執行速度提升約11%。第二,當解碼器在儲存事前對數概似比(Prior Log Likelihood Ratio)的同時,即運算第一個檢查點(Check Node),此舉可節省執行所需的周期數約3%。第三,我們改進了偵測收斂的方法,而省去儲存上個迴圈的解碼結果,故可以節省原儲存對數概似比記憶體需求的11%。最後我們將跟過去的文獻做比較,在802.11n的規範下,我們的解碼器面積比較小且節省功率消耗。 Gallager published Low Density Parity Check (LDPC) code in 1963. Since the computation power is so weak at that time, LDPC has not been paid much attention. However, LDPC has become an important technique because of advanced semiconductor technology that increases gradually the computation power. The architecture of LDPC decoder can be simply divided into two kinds: fully-parallel and partial-parallel schemes. There are some variations on the partial-parallel schemes depending on their parallelization methods. In this Thesis, we used a block-serial architecture for the implementation of an LDPC decoder, which has three improvements compared with previous work proposed by Xiang. The first is to shorten the critical path by reordering the process step and the storing step, which can facilitate an 11% improvement in the clock rate. The second is that the decoder updates the first check node message while it is storing the Log-Likelihood Ratio (LLR) data. As a result, the proposed design saves 3% clock cycles than the previous work. The third is that this work improves the algorithm of detecting convergence, which can avoid saving the last iteration result. Therefore, the storage space required to save the LLR can be reduced to 11% of the original size. Finally, the performance evaluation with other previous works was made to validate that the proposed design is having smaller chip area and less power dissipation. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/59004 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
File | Size | Format | |
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ntu-102-1.pdf Restricted Access | 5.25 MB | Adobe PDF |
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