OpenCL在可程式邏輯陣列上運算使用多埠共享記憶體

Abstract

針對 FPGA 所做的高階合成方法已被廣泛地運用於高效能運算上。 隨著 OpenCL 的推出，一些高階合成的研究已經轉向將 OpenCL 引入 FPGA 來使用。本論文提出一個適用於 FPGA 的 OpenCL 架構並且著 重於記憶體存取的改善以達成最佳效能的目標。在 OpenCL 的計算區 塊裡，執行時間與區域記憶體的存取延遲時間總是存在著一個線性關 係，而這延遲時間一般會以增加平行工作量來彌補的，然而這樣的方 法很容易地就會耗盡 FPGA 上的資源。因此本文使用無衝突的多埠記 憶體，藉此將區域記憶體的存取延遲時間減至最少。實驗結果顯示多 埠記憶體能成功地提高運算速度並減少所需的平行工作量到一個可行 值來提供最高產量。

High-Level Synthesis (HLS) targeting FPGAs has been widely used for high performance computing. With the introduction of OpenCL, some of the HLS research have shifted towards bringing OpenCL to FPGAs. This thesis presents an OpenCL architecture for FPGAs and focuses on memory access improvements with the goal of achieving optimal performance. In OpenCL compute blocks, there is usually a linear relation between computation time and local memory access latency. This latency is normally hidden by increas- ing the parallel workload. However, with such an approach, target FPGA device could easily run out of resources. In this work, conflict-free multi- ported memories have been used instead to minimize local memory access latency. Experiments show that multiported memories can successfully increase computation speed and reduce the required parallel workload for max- imum throughput to practical amounts.