具變壓器回授的K-Band低功耗頻率合成器與寬頻除頻器之研製

Abstract

高頻以及高速鎖相迴路在現代有線或無線通訊系統中扮演了一個重要的角色。本篇論文，為克服互補式金氧半導體製程限制，提出了一系列創新的電路架構，對於CMOS毫米波的壓控振盪器、頻率合成器與除頻器做出相關之設計與分析。 在第二章中，低功耗、適用於K-Band的壓控振盪器被提出，適合應用在可攜式RF前端電路。該壓控振盪器因為沒有使用Q值較差的變容二極體的關係，在相位雜訊方面的特性將有所提升。且此壓控振盪器為了達到高F.o.M.的設計目標，採用了互補式的變壓器回授架構來達到低功耗的特性。 在第三章中，提出一個K-Band低功耗頻率合成器，應用於汽車防撞雷達系統之24-GHz的RF前端電路。該頻率合成器採用了變壓器回授的壓控振盪器和疊接式除頻器，故可以達到低功耗的特性。此外，針對頻率合成器裡的電路成員，壓控振盪器、CML除頻器、多模除數除頻器、相位頻率偵測器、充電汞...等電路做了適當的分析與研究。 在第四章中，寬頻的疊接式的注入式鎖定除頻器和CML除頻器被提出。透過移除兩除頻器中間的寄生效應來達到寬頻與低功耗的特性，並達到高F.o.M.的設計目標。所提出的電路操作頻率在0dBm注入功率下可以從14到37GHz的模擬結果，是使用65奈米的金氧半導體製程，而功耗為2毫瓦。 論文的第一章和第五章分別是論文的動機介紹和本碩士論文完成的工作結論。

In present generation, high-frequency and high-speed phase-locked loop plays an important role in wireline or wireless communication systems. To alleviate the limitations imposed on CMOS technique, some design techniques are developed for CMOS millimeter-wave integrated circuits, such as voltage-controlled oscillator, frequency synthesizer and frequency divider in this thesis. In Chapter 2, a low power K-Band voltage-controlled oscillator is proposed for RF frontends circuits. Because of without using the tuning varactors, which are low quality factor device, the VCO would have better phase noise performance. In order to have high F.o.M. performance, the complementary VCO adopts the three-coil transformer-feedback to have low dc power consumption. In Chapter 3, a low power K-Band frequency synthesizer is proposed for 24-GHz frontend circuit design of collision avoidance radar system. The circuit employs a transformer-feedback voltage-controlled oscillator and cascoded frequency divider, so it can achieve low power design. Furthermore, we focus on the design and analysis of the subcircuits, such as voltage-controlled oscillator, CML frequency divider, multi-modular divider, phase frequency detector, charge pump, etc. In Chapter 4, a wide locking range frequency divider of injection-locked frequency divider and CML divider is presented. By removing the parasitic capacitors between two dividers to widen locking range, lower dc power consumption and achieve high F.o.M. performance. The cascoded frequency divider achieves locking range from 14 GHz to 37 GHz at 0 dBm injection power and is implemented in 65nm CMOS technology. The total power consumption is 2 mW. Chapter 1 and Chapter 5 are the introduction and the conclusion about this thesis, respectively.