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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/57170完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃天偉(Tian-Wei Huang) | |
| dc.contributor.author | Hsin-Chuan Chen | en |
| dc.contributor.author | 陳信全 | zh_TW |
| dc.date.accessioned | 2021-06-16T06:36:48Z | - |
| dc.date.available | 2024-12-31 | |
| dc.date.copyright | 2019-03-22 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-07-31 | |
| dc.identifier.citation | [1]K. Kwok and H. C. Luong, 'Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,' IEEE Journal of Solid-State Circuits, vol. 40, no.3, pp.652-660, March 2005.
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Huang, 'An Ultra Low-Power 24GHz Phase-Locked-Loop with Low Phase-Noise VCO Embedded in 0.18μm CMOS Process,' Proceedings of the Asia-Pacific Microwave Conference, 2011. [14]Min Huang, Chia-Hui Yu, Jeng-Han Tsai, and Tian-Wei Huang, 'A Low-Power 24GHz Phase Locked Loop with Gain-Boosted Charge Pump Embedded in 0.18μm CMOS Technology,' Proceedings of the Asia-Pacific Microwave Conference, 2012. [15]A. W. L. Ng, G. C. T. Leung, K.-C. Kwok, L. L. K. Leung, and H. C. Luong, 'A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18μm CMOS process,' IEEE J. of Solid-State Circuits, vol.41, no.6, pp.1236-1244, Jun, 2006. [16]J. Kim, J. K. Kim, B. J. Lee, N. Kim, D. K. Jeong, and W. Kim, 'A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS,' IEEE J. of Solid-State Circuit, vol.41, no.4, pp.899~908, Apr, 2006. [17]Chunyuan Zhou, Lei Zhang, Dongxu Yang, Yan Wang, Zhiping Yu, He Qian, 'A 24-GHz Fully Integrated Phase-Locked Loop for 60-GHz Beamforming,' Solid-State and Integrated Circuit Technology, 2012. [18]O. Richard, A.Siligaris, F. Badets, C. Dehos, C. Dufis, P. Busson, P. Vincent, D. Belot, and P. Urard, 'A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for Wireless HD Applications,' in IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2010, pp.252-253. [19]B. Razavi, 'A study of injection locking and pulling in oscillators,' IEEE, J. Solid-State Circuits, vol.39, no.9, Sep 2004. [20]H. R. Rategh and Thomas H. Lee, 'Superharmonic Injection-Locked Frequency Dividers,' IEEE Journal of Solid-State Circuits, vol.34, No.6, pp. 813-821 Jun. 1999. [21]M. Tiebout, 'A CMOS Direct Injection-Locked Oscillator Topology as High-Frequency Low-Power Frequency Divider,' IEEE Journal of Solid-State Circuits, vol.39, no.7, pp.1170-1174, Jul. 2004. [22]C.-Y. Wu and C.-Y. Yu, 'Design and analysis of a millimeter-wave direct injection-locked frequency divider withlarge frequency locking range,' IEEE Transactions on Microwave Theory and Techniques, vol.55, no.8, pp.1649-1658, August 2007. [23]Z.-D. Huang, C.-Y. Wu and B.-C. Huang, 'Design of 24-GHz 0.8-V 1.51-mW coupling current-mode injection-locked frequency divider with wide locking range,' IEEE Trans. Microw. Theory Tech., vol.57, pp.1948-1958, Aug. 2009. [24]Yen-Hung Kuo, Jeng-Han Tsai, Hong-Yeh Chang, and Tian-Wei Huang, “Design and Analysis of a 77.3% Locking-Range Divde-by-4 Frequency Divider,” in IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL.59, NO.10, OCT 2011. [25]C.-C. Chen, H.-W. Tsao, and H. Wang, “Design and analysis of CMOS frequency dividers with wide input locking ranges,” IEEE Trans. Microw. Theory Tech., VOL.57, NO.12, pp.3060-3069, Dec, 2009. [26]S.-H. Lee, S.-L. Jang, and Y.-H. Chung, “A low voltage divide-by-4 injection locked frequency divider with quadrature outputs,” IEEE Microw. Wireless Compon. Lett., vol.17, no.5, pp.373-375, May 2007. [27]劉深淵, 楊清淵 著, '鎖相迴路,' 滄海書局出版. [28]Behzad Razavi, 'RF Microelectronics,' Second Edition. [29]Z. Zhujin, L. Ning, L. Wei, R. Junyan, 'A power-optimized CMOS quadrature VCO with wide-tuning range for UWB Receivers,' ISCAS, Oct. 2007, pp. 437-440. [30]J.-C. Chien and L.-H. Lu '40 GHz wide-locking-range regenerative frequency divider and low-phase-noise balanced VCO in 0.18-μm CMOS', IEEE ISSCC Dig. Tech. Papers, pp.544 -545 2007 [31]C.-C. Chen, H.-W. Tsao and H. Wang 'Design and analysis of CMOS frequency dividers with wide input locking ranges', IEEE Trans. Microw. Theory Tech., vol. 57, pp.3060 -3069 2009 [32]黃瀞萱, '0.5-V 1.25-GHz鎖相迴路之設計與實現,' 國立中央大學電機工程所碩士論文. [33]C.-K. Hsieh, K.-Y. Kao and K.-Y. Lin, 'An ultra-low power CMOS complementary VCO using three-coil transformer feedback,' in 2009 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., June 2009, pp. 7-9. [34]李煥文, '應用於超寬頻之低雜訊互補金氧半壓控振盪器設計,' 私立逢甲大學電子工程學系碩士班碩士論文. [35]Kuan-Chung Lu, Fu-Kang Wang, and Tzyy-Sheng Horng, 'Ultralow Ohase Noise and Wideband CMOS VCO Using Symmetrical Body-Bias PMOS Varactors,' IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL.23, NO.2, FEB. 2013. [36]K. Kwok and H. Luong, 'Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,' IEEE J. Solid-State Circuits, vol. 40, no. 3, Mar. 2005. [37]王銓慶, '應用於MB-OFDM Mode-1UWB接收機之CMOS壓控振盪器與頻率合成器的研製,' 國立成功大學電腦與通信工程研究所碩士論文. [38]余家輝, '具變壓器回授的Ka-Band低功耗頻率合成器與具可調式穩壓電路的壓控振盪器之研製,' 國立台灣大學電信工程研究所碩士論文. [39]郭彥宏, '寬頻除頻器和數位校正之射頻電路的設計和分析,' 國立台灣大學電信工程研究所博士論文. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/57170 | - |
| dc.description.abstract | 高頻以及高速鎖相迴路在現代有線或無線通訊系統中扮演了一個重要的角色。本篇論文，為克服互補式金氧半導體製程限制，提出了一系列創新的電路架構，對於CMOS毫米波的壓控振盪器、頻率合成器與除頻器做出相關之設計與分析。
在第二章中，低功耗、適用於K-Band的壓控振盪器被提出，適合應用在可攜式RF前端電路。該壓控振盪器因為沒有使用Q值較差的變容二極體的關係，在相位雜訊方面的特性將有所提升。且此壓控振盪器為了達到高F.o.M.的設計目標，採用了互補式的變壓器回授架構來達到低功耗的特性。 在第三章中，提出一個K-Band低功耗頻率合成器，應用於汽車防撞雷達系統之24-GHz的RF前端電路。該頻率合成器採用了變壓器回授的壓控振盪器和疊接式除頻器，故可以達到低功耗的特性。此外，針對頻率合成器裡的電路成員，壓控振盪器、CML除頻器、多模除數除頻器、相位頻率偵測器、充電汞...等電路做了適當的分析與研究。 在第四章中，寬頻的疊接式的注入式鎖定除頻器和CML除頻器被提出。透過移除兩除頻器中間的寄生效應來達到寬頻與低功耗的特性，並達到高F.o.M.的設計目標。所提出的電路操作頻率在0dBm注入功率下可以從14到37GHz的模擬結果，是使用65奈米的金氧半導體製程，而功耗為2毫瓦。 論文的第一章和第五章分別是論文的動機介紹和本碩士論文完成的工作結論。 | zh_TW |
| dc.description.abstract | In present generation, high-frequency and high-speed phase-locked loop plays an important role in wireline or wireless communication systems. To alleviate the limitations imposed on CMOS technique, some design techniques are developed for CMOS millimeter-wave integrated circuits, such as voltage-controlled oscillator, frequency synthesizer and frequency divider in this thesis.
In Chapter 2, a low power K-Band voltage-controlled oscillator is proposed for RF frontends circuits. Because of without using the tuning varactors, which are low quality factor device, the VCO would have better phase noise performance. In order to have high F.o.M. performance, the complementary VCO adopts the three-coil transformer-feedback to have low dc power consumption. In Chapter 3, a low power K-Band frequency synthesizer is proposed for 24-GHz frontend circuit design of collision avoidance radar system. The circuit employs a transformer-feedback voltage-controlled oscillator and cascoded frequency divider, so it can achieve low power design. Furthermore, we focus on the design and analysis of the subcircuits, such as voltage-controlled oscillator, CML frequency divider, multi-modular divider, phase frequency detector, charge pump, etc. In Chapter 4, a wide locking range frequency divider of injection-locked frequency divider and CML divider is presented. By removing the parasitic capacitors between two dividers to widen locking range, lower dc power consumption and achieve high F.o.M. performance. The cascoded frequency divider achieves locking range from 14 GHz to 37 GHz at 0 dBm injection power and is implemented in 65nm CMOS technology. The total power consumption is 2 mW. Chapter 1 and Chapter 5 are the introduction and the conclusion about this thesis, respectively. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T06:36:48Z (GMT). No. of bitstreams: 1 ntu-103-R01942027-1.pdf: 5223660 bytes, checksum: 95c84c51e6966283a07adda4efe9d956 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 iii ABSTRACT iv CONTENTS vi LIST OF FIGURES ix LIST OF TABLES xv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of Thesis 2 Chapter 2 A Low-Power K-Band Transformer- Feedback Complementary VCO with Three-Coil Transformer 3 2.1 Introduction 3 2.2 Analysis of Voltage-Controlled Oscillator 5 2.2.1 Voltage-Controlled Oscillator Basics 5 2.2.2 Oscillators Comparison 9 2.2.3 Noise of Bias Current Source 11 2.2.4 Transformer-Feedback Technique 13 2.3 Analysis of Phase Noise 17 2.3.1 Phase Noise Basics 17 2.3.2 Effect of White Noise and Flicker Noise 19 2.4 Proposed Architecture and Circuit Design of Complementary TF-VCO..... 22 2.5 Design of VCO 30 2.6 Simulation and Measurement of Complementary TF-VCO 31 2.6.1 Simulation Results 31 2.6.2 Measurement 34 2.7 Discussion 39 2.8 Summery 42 Chapter 3 A K-Band Frequency Synthesizer Using Push-Push Transformer-Feedback VCO in 180-nm CMOS Technology 44 3.1 Introduction 44 3.2 Proposed Architecture and Circuit Design of Frequency Synthesizer 45 3.2.1 Frequency Plan 45 3.2.2 Phase Frequency Detector (PFD) 46 3.2.3 Charge Pump (CP) 48 3.2.4 Loop Filter (LPF) 50 3.2.5 Push-Push Transformer-Feedback Voltage-Controlled Oscillator (Push-Push TF-VCO) 57 3.2.6 Cascoded Current Mode Logic (CML) Divider 62 3.2.7 Multi-Modulus Frequency Divider 65 3.2.8 True-Single-Phase-Clock (TSPC) Divider 66 3.3 Phase Noise Analysis of Phase-Locked Loop 68 3.4 Design of Phase-Locked Loop 71 3.5 Simulation and Measurement of Frequency Synthesizer 71 3.5.1 Simulation Results 71 3.5.2 Measurement 84 3.6 Discussion 88 3.7 Summery 90 Chapter 4 A Wide Locking Range Divide-by-4 Frequency Divider in TSMC 65nm 92 4.1 Introduction 92 4.2 Analysis of Frequency Divider. 93 4.2.1 Injection-Locked Frequency Divider (ILFD). 93 4.2.2 Current Mode Logic (CML) Divider. 98 4.2.3 Dynamic Logic 102 4.3 Proposed Architecture and Circuit Design of Frequency Divider 103 4.4 Design of Divide-by-4 Frequency Divider 106 4.5 Simulation of Frequency Divider 106 4.6 Summery 108 Chapter 5 Conclusion 110 REFERENCE 112 PUBLICATIONS 117 | |
| dc.language.iso | zh-TW | |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | 頻率合成器 | zh_TW |
| dc.subject | 壓控振盪器 | zh_TW |
| dc.subject | 注入式鎖定除頻器 | zh_TW |
| dc.subject | 變壓器回授 | zh_TW |
| dc.subject | frequency synthesizer | en |
| dc.subject | transformer-feedback | en |
| dc.subject | injection-locked frequency divider | en |
| dc.subject | phase-locked loop | en |
| dc.subject | voltage-controlled oscillator | en |
| dc.title | 具變壓器回授的K-Band低功耗頻率合成器與寬頻除頻器之研製 | zh_TW |
| dc.title | Design and Analysis of K-Band Low Power Transformer- Feedback Frequency Synthesizer and Wide Locking Range Frequency Divider | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張鴻埜(Hong-Yeh Chang),蔡政翰(Jeng-Han Tsai) | |
| dc.subject.keyword | 鎖相迴路,頻率合成器,壓控振盪器,注入式鎖定除頻器,變壓器回授, | zh_TW |
| dc.subject.keyword | phase-locked loop,frequency synthesizer,voltage-controlled oscillator,injection-locked frequency divider,transformer-feedback, | en |
| dc.relation.page | 117 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2014-08-01 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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